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Recent content by vlsi_eda_guy

  1. V

    I would like to know few things on testing a chip.

    Tester Tim Hi, I would like to know few things on testing a chip. How much time it generally takes for testing a chip on ATE? How is the chip tested at wafer leve, die or packaged chip? -vlsi_eda_guy
  2. V

    What is the compression ratio and how to fix the compression ratio for any design?

    Re: Compression ratio HI , Read this one **broken link removed** -cheers vlsi_eda_guy
  3. V

    What is the effect of computing pwr without setting toggle rate?

    saif toggle rate There is a default value for both the toggle rate and static probability. THe tool will use that power_default_toggle_rate = "0.1" power_default_static_probability = "0.5" -cheers vlsi_eda_guy
  4. V

    What is the compression ratio and how to fix the compression ratio for any design?

    Re: Compression ratio Hi kiran, The compression ratio in DFT is basically used for TAT and TDV TAT : Tester application Time TDV : Test data volume. ( Size of the patterns) It is the reduction in these two number when compared to a design which has just the scan chains and no compression...
  5. V

    How to choose the number of Scan-in and Scan-out?

    Re: Scan chains Santosh, can you elaborate how the number of scan chains is controlled by " test time( cost of the device per million parts) and number of flops in the chain". Please talk about a practical design. Dont say that a design with 5 flops cannot have 6 chains. Also, I would...
  6. V

    How to choose the number of Scan-in and Scan-out?

    Re: Scan chains well 500 is a hypothetical number ,but yes if the tester can support 500 scan chains then you will get the best results ( tester Applicaton Time ) with 500 scan chians... Also, your chip should have 1000+ pins ;-)
  7. V

    why the DFT test_clock ;s duty cycle is 10%,not 50%?

    you can not have it as {0 50 } , beacause the PI has to be forced from Tester before the clock can come. Again you have to give some time for the PI to settle before you can give the clock. If not you will get setup violations.... Also, if you are doing pre-clock strobe then you will give...
  8. V

    Can we have the scan shift frequency the same as functional frequency?

    Re: Scan shift frequency Hi Jaanki, The maximum shift frequency will depend on what is the maximum peak power, the chip can support. When you are shifting the data on the scan chain, all the flops in the chains are operational the same time. The peak power requirment goes high, also too...
  9. V

    What is the difference bettween fault collapsing and fault uncollapsing?

    Re: Fault collapsing Hi Kiranks9, By fault collapsing we are trying to reduce the number of faults on which ATPG will run. To understand fault collapsing consider a AND gate. In all it will have 6 faults. Pin A,B and Z stuck-at-0 and stuck-at-1 Now consider the fault Z -stuck-at-0 ...
  10. V

    How to choose the number of Scan-in and Scan-out?

    Re: Scan chains This has to be decided by the tester you plan to use. How many scan channels it can support. MOre the number of scan chains better it is.... If you have multiple tester, you can use multimode where you can have different modes each having different number of scan chains...
  11. V

    What will fault simulation do while generating pattern?

    Re: Fault simulation Hi, Badola has given the correct answer from functional pattern point of view. If you want to know what it does during pattern generation then you have to understand the way the patterns are generated. Pattern generation is a two step process, 1. Test Generator...
  12. V

    How to balance the scan chains?

    Re: Scan chain balance If you have multiple clocks in the testmode, then to have a balance chains you have to make sure that you allow clock mixing in the scan chains. At the boundary where the clocks changes a lockup latch should be inserted. -cheers Anand
  13. V

    Launch and capture in At-speed mode

    Hi, For at-speed fault there is a requirement that we launch the fault. By launching it means that we give a transition at the fault site. So for slow-to-rise fault, the launch will be to change the value from 0 to 1. Once the fault has been launched , the changed value is captured At-speed in...
  14. V

    why scan chain is deleted before placement and reconnected..

    Re: why scan chain is deleted before placement and reconnect Hi, In intial routing the scan chains are routed in an alphanumeric manner. In placement the routing is done considering the routing and clock optimization and other factors... Two slides attached to give illustration... -cheers...
  15. V

    Why Full Scan called combinational?

    hi Shakti, Once your design is fully scanned, the flops on the scan chains act like virtual inputs and outputs. To access any part of the logic you can load the chains with scan enable high. Similarly any flops value can be taken out during the unload of the chain. The data doesn't have to go...
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