Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vladimir1984

  1. V

    papers about Analog IC design to share

    Hello all! Is there an error on paga 15, figure 15. There is written 0.5LSB error, INL = 0.2LSB. Is this an error or I don't understand something? Thanks
  2. V

    simple delay circuit design 10 ns

    rc dac Yes, of course I can share with you. I have one pdf, in which you can find both configurations, caps for MSBs, resistors for LSBs, and resistors for MSB, caps for LSB. You can find the schemes at the end of pdf, data converters chapter.
  3. V

    How to measure Gm of FET in IC 5?

    Re: How to measure Gm? you can calculate gm by the fromula, which you can find in any book and the PDK document of technology you use Regards
  4. V

    Question on 2 stage buffer design

    dear mike_behan, I can you advise to read the amplifiers chapter in Jacob Baker 2-nd edition book, may help
  5. V

    Process corners,Voltage,temperature

    you need to decrease your reqirements in the specification, or try to find out another decision, which allow to achieve your requirements. First of all you may determine can you achieve this requirements with your technology or it is absolutely impossible.
  6. V

    tsmc_.18 proce$$ description

    Is it possible to download the TSMC PDK from the inet site?
  7. V

    Full scale error for ADC

    If the full-scale error is so critical for your specification, at first try to use offset concellation. Did you use an offset concellation in your ADC?
  8. V

    What is the minimum LNA noise figure achievable in CMOS 0.18

    Re: CMOS LNA I think it is almost impossible to achieve 0.9db noise with the CMOS technology, especially I mean repetition production, not experimantal samples
  9. V

    Looking for a good CV template

    Hi everybody! I need a good CV example, a CV with successfull found job is desirable. Thanks
  10. V

    DC-offset cancellation and DC-offset voltage

    Re: offset cancellation My simulation in Cadence showed that the offset cancellation using the negative feedback doesn't depend on DC level of offset voltage. Added after 5 minutes: I recommend you to read this article. Hope it will help you a lot.
  11. V

    SAR ADC with self-calibration technique

    self calibration sar adc Hi everybody! Now I design a 12-bit SAR ADC with capacitor ratio self-calibration. Because technology, I use, doesn't allow to reach more than 10 bit accuracy even with the superior matchnig of capacitors. Does anybody have experience with the ADCs with...
  12. V

    Please explain me the Monte Carlo process on these pictures

    Re: Monte Carlo question I think it's mean that parameter L is deeviate with standard Gauss distribution, with absolute value 0.01% from 8u. The same for the second picture.
  13. V

    i need TSMC CMOS 0.18m for pspice simulater, pls

    The homepage of University of California https://www.berkeley.edu/
  14. V

    What is the difference between Flash and SONOS?

    Flash vs. SONOS Hello everybody? What is the difference between Flash and SONOS? Regards, Vladimir
  15. V

    Need Suggestion on Op-amp Testbench

    In Allen you can find a schematics of testbenches used in simulations of OpAmps
See more

Part and Inventory Search

Back
Top