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Recent content by vjkr

  1. V

    calculating delays for COMBINATIONAL & SEQUENTIAL designs

    @barry: thanks i didnt know the first point. . . . But problem remains as it is(with varied code) For your example, assuming the clk statement is fixed, you have the prop delay of the register (CLK->a1,a2,a3) + the comb. delay of the adder (a+b+c) (I'm assuming a,b,c are the outputs of the...
  2. V

    calculating delays for COMBINATIONAL & SEQUENTIAL designs

    Hi, i ve this code..................................................................................................................................................................... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.numeric_std.ALL; entity...
  3. V

    [SOLVED] vhdl code : help regarding port mapping

    Thanks a ton, TrickyDicky;xtcx. :-)
  4. V

    [SOLVED] vhdl code : help regarding port mapping

    thanks, what about the implications on field(board)......? I ve been implementing the design in mixed style; STRUCTURAL and BEHAVIORAL styles. For the points u made; I inferred that during runtime; i will be getting the outputs from all modules , but i shall select my needed data as on...
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    [SOLVED] vhdl code : help regarding port mapping

    hi... i ve written certain modules in vhdl; Now i ve to SELECT THE MODULES(components) for operations BASED ON SOME CODITIONS. 1. But i learnt port mapping cant be done for conditions... (port mapping cant be done inside process) 2. are there any concurrent conditional' port mapping statements'...
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