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Recent content by vivekrajeev

  1. V

    DRC error in 45 nm in calibre

    hi As the tech node goes on decreasing your rules keep on increasing We use poly in only one orientation We maintaion poly -poly pitch which is constant We use end caps OR fillers at the end of every row below 45nm
  2. V

    what is PMET layer in 28nm tsmc technology ? it covers entire p+ implantation. ?

    Hi what is PMET layer in 28nm tsmc technology ? it covers entire p+ implantation. ?May i know what is its use ? Thanks Vivek
  3. V

    how do i convert gds back to def if i have netlist with me ? is ti possible

    Hi I have a scenario where i have some changes made to GDS and want to revert back to def. Is it possible ? I have netlist with me. Scenario: I have solved some DRC on M8 layer and some other person has solved some DRC on M2 layer. Now we want to merge those...
  4. V

    why is that we take clock skew ast 20% of the clock period??

    Hi i do not understand how people arrived at the value that skew should be 20% of clock period. Could you please answer each question with number in detail. I would be so grateful to you 1. Also one more doubt does the area of the design influence the insertion delay ??? 2...
  5. V

    what does a decap cell contain ?

    thanks i opened the layout and i find the same. CPO is contact for poly right ?? poly is connected to VSS in this so it forms a gate type decap where the upper plate is POLY and lower is lower is BULK. am i right ??
  6. V

    what does a decap cell contain ?

    hos does a poly connected to VDD and source /drain connected to VSS work as decap
  7. V

    what is SR_DPO layer what is it used for

    Hi what is seal ring ? what is SR_DPO ? how is it different from normal PO. i saw a filler cell layout and i find DPO running over OD with its source and drain unconnected. Can we have such unconnnected transistors??? Please help me out of this confusion
  8. V

    [SOLVED] in physical design why is that we find VDD tap cell but not VSS tap cell.

    in physical design why is that we find VDD tap cell but not VSS tap cell.
  9. V

    floating inputs and outputs

    Can i get more information how it picks up charges can you direct me to some material please :)
  10. V

    floating inputs and outputs

    Hi why are floating inputs should not be there could some body tell the reason ???
  11. V

    what does a decap cell contain ?

    What does layout of a decap cell contain inside. how do they work . Please explain
  12. V

    why there should be n well spacing

    So you say that it forms an extra npn transistor which is unintended right? Thats the reason we give spacign and one more is the manufacturability thing. Thanks for the answer dick
  13. V

    why cant we have unconnected source or drain ?

    Yes i mean unconnected drain and source of mosfet. What happens if such a scenario is there ? I
  14. V

    [SOLVED] why is that every row should end with endcap

    Hi how can endcap prevent routing outside the macro? I dint get it. Could you please elaborate
  15. V

    [SOLVED] why is that every row should end with endcap

    Hi Guys I have a doubt why is that every row should end with an endcap. What happens if we dont have endcap. Whats inside end cap
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