Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vivek_raj_verma

  1. V

    What is the physical meaning of Pole and Zero?

    physical significance of zeros and poles this has been always a matter of confusion to me whenever i sit and think about poles and zeros. And still after reading all above discussions......i think somewhere, something is missing..... Is it just mathematics...
  2. V

    PMOS diff pair as 1st stage and nmos common source 2nd stage

    I think its better to use Nmos op amp. but depending on situation like whats the input common mode ...we need to decide which will be best in terms of OVD and SAT margins. Second stage must be a gain stage and NMOS always has adv of smaller size (so smaller parasitics) over Pmos counter part.
  3. V

    Why Vdd is also the AC ground when doing small signal equivalent circuit analysis?

    a simple question why do we open the dc currrent sources ??
  4. V

    [SOLVED] Why vdsat is not equal to vgs-vth?

    vgs-vth hi there, see the equation of Vdsat in ur models. Also i wnat to know about above values.. at what point u got it. r they results of any simulaton
  5. V

    stability analysis with step response and AC loop analysis

    hi there, i think there might be some mistake when u r breaking the loop for stability analysis. Can u post ur cir file in which u r doing this.. then probaly i may help u. Ur dc operating point of circuit should not change when u r doing an AC analysis. what r u doing for this ???
  6. V

    Why we usually set ac=1v?

    hi there, AC = 1 volts eases the computation. Gain = vout/vin and u can see when u write vdb(vout) it gives u gain (Vout/vin) at that node. It does not affect any other thing. u can write whatever u want here but in that case u have to see how can u extract gain from the simulator u r using???
  7. V

    My Grief - Can someone show me a way?

    Hi there, Its absurd to make u learn all those things. Now a days where there are concepts of open book exams r growing up, these is abosultely rubbish. But my frnd at some places its like that only. so just see the prev Q paper and learn the imp thngs only. So that u can get good marks...
  8. V

    Layout fundamentals for beginners

    Layout Fundamentals book by uyemura may be of great help.
  9. V

    How to generate a layout from architecture implemented using VHDL?

    VHDL to LAYOUT thanks smith, U r right. Cadence can give me a layout from vhdl. But i dont have that tool in the lab. so i was looking for an alternative. Also as u have said i can do in tanner too using hierarchy but surely that will consume more time. It was my minor project only so i...
  10. V

    u(-t) = or not = to - u(t) ?

    Hi, If u want a proof. I think the proof given by Tantoun2004 is correct. Otherwise there is no doubt that they r diff. as u can see them from their plot easily. vicky
  11. V

    How to generate a layout from architecture implemented using VHDL?

    VHDL to LAYOUT thanks for the suggestions frnds. I have the ISE 7.1 tools in my institute lab so that is not a problem, the problem is to generate a layout as we do in cadence and t spice etc. So how that can be generated from VHDL code. There is a tool in cadence that can genrate this...
  12. V

    How to generate a layout from architecture implemented using VHDL?

    VHDL to LAYOUT Hi there, Is there anyone more who can help me on this ????? vivek
  13. V

    Problem with cable connection while programming Xilinx FPGA kit

    Re: help needed thanks , i ll be posting the messeges what it gives and the xilinx kit information soon.
  14. V

    Problem with cable connection while programming Xilinx FPGA kit

    hi there, I ve encoutered one problem while programming xilinx FPGA kit. It shows cable is not connected. when i do autodetect cable it shows cable is connected but when i say program then again it says that cable isnot connected. what cud be the problem??? help, i m new to it. programming...
  15. V

    Best books on circuit analysis, basic electronics, electronic devices etc.

    asic book hi, NO one has mentioned the famous book fo digital ciruits and design. MORRIS Mano Added after 2 minutes: forgot to mention. for VLSI technology--S M Sze digital cmos intgated ckts-kang and leblebici also one book is on digital design by Wayner wolf
See more

Part and Inventory Search

Back
Top