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Recent content by vivek4m

  1. V

    Time delay in SV Assertions

    Thanks a lot. I think it will help me :D .
  2. V

    Time delay in SV Assertions

    Hi Friends, I need to use a time delay (not clock cycles delay) in one of my systemverilog assertions. It will be a great help if anyone could give me an insight of whether I can do it or not? If yes, then how can I do it. I am looking for a way to implement something like this: property...
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    Syatemverilog VCS cov report

    Hi Ajeetha, Aji, Where to run the command urg -dir simv.vdb ? I put it in my run_vcs.sh script in the end and I got a message urg: command not found I am using DVE console to run the simulations. On the DVE console command prompt also it says invalid command name "urg" Do I need some special...
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    task $isunknown in systemverilog

    Hi People, I have a question regarding $isunknown task of systemverilog. Can we pass multi-bit arguments to this task or it accepts only single bit variables? Is following a valid statement: assert !($isunknown({clk, regA[15:0], data_in, shiftr_out, varB}); Thanks & Regards Vivek
  5. V

    What is a "callback" in Systemverilog?

    what is callback in system verilog Callbacks are used by tests to add new functionality to the driver without editing the driver class. Following types of new functionality can be added using callbacks: ? Inject errors ? Drop the transaction ? Delay the transaction ? Synchronize this...
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    Any course on SystemVerilog

    system verilog training in bangalore Hi Pradeep, I am also looking for a good course in system verilog and got to know about CVC training center in bangalore. (cvc.training@gmail.com, training@noveldv.com, 9916176014 ) I have not yet tried this course as I am looking for a system verilog...
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    Interview question about a FIFO depth

    depth of fifo to avoid an overflow, you need the depth to be 25 atleast!
  8. V

    Significance of TOGGLE COVERAGE

    edaboard toggle coverage Hi Spartan, Toggle Coverage is basically a check which tells the percentage of the I/Os of your module toggling with your test suite. If your test suite is exercising all the boundary signals of your module and none of the I/Os are tied or left dangling, then your...
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