Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
for checking the intermediate gain & phase plots you can run ac analysis using 3 amp structure or using the res bias.
Here you need to ensure that the loop bias is maintained properly.
In 3 amp structure, 1 amp is used for bias other for load and the other will be tested
Re: what happens if emitter-base & base-collector junctions are forward biased with 0
no if both the junctions are forward biased the BJt acts as a ON swith. if input junction is forward biased and output junction is reverse biased then the BJT will be in saturation region.
when it is a on...
Break the loop at the gate of the power fet and apply the signal there and see the open loop response. but make sure that the biasing of the circuit is still maintained.
Generally the stability simulation is done by modeling few components. Becoz ac analysis is generally done for unsaturated...
Generally psrr means the gain from the input to output divided by the gain from the supply to the output. But for an LDO the input itself is the power supply so i think it can be done.
the transit frequency gives the intrinsic (maximum) speed of the mosfet;
it also means that beyond that frequency the device cant be used as a voltage amplifier;;
have u simulated the memory cell using the s2i technique, if yes then u will not have any problem in simualting the integrator as well;;
specify ur technology in which ur working.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
