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Recent content by vinod488

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    VLSI industry in INDIA

    Hi Nowadays VLSI market is not good,,,, Its not like Software All companies are in LOSS that why no company having requirements,,, Let's see wht will hapen
  2. V

    PLease Vote: Electronics Engineer Vs Computer Engineer

    Electronics is far better than SW
  3. V

    Fresherer ,,,analog questions required,,,,its urgent,,,,

    Hi i am fresherer,,,i want know which type of questions will come in interview based on analog,,,, Regards, Vinod
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    Critical path in SRAM

    setup time read sram hi, Thanks for ur reply. Canu u tell me the which material is best for Memories with access time and critical path calculations. Regards,
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    Simple verilog question

    hi, I Think a<=0 comes out. Sometimes it depends on simulator which ur using. Regards, Vinod
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    Exercise problems in FSM

    hi, Thanks to all for this great response. Regards, Vinod
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    Block level architecture of Divide by 11 circuit

    Re: Divide by 11 circuit hi, Divide by 11 u can do by using 4 T Flipflops, take output of 1,3,4 FFs and give it to NAND gate,give NAND output to reset input of all Flipflops. Hope this helps. Vinod
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    setup time +ve or -ve?

    hi, Go to vlsibank.com/forum here -ve setup and -ve hold time are clearly explained
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    Critical path in SRAM

    critical path modeling of sram Hi, Anyone can tell what is critical path in SRAM. What are conditions we have to take care for proper functioning.
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    Request: Plz list VLSI companies List with Address & Mai

    list of vlsi companies in india Hi All, Any one can provide the VLSI company List with details.I want this information. Thanks in advacne. Vinod
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    difference between useful skew and zero skew

    Hi, If system having Zero Skew hold violation is less. Useful skew means helps to increase the frequency of operation same time it should not violate hold constraint. Regards, Vinod
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    VHDL Book for this kind of Questions:

    hi, You can find theory and procedure to solve FSM in Digital Logic by Stephen Brown by using VHDL or by using Verilog. In FPGA LUT point of view u can find in Digital System By Charles ROTH.
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    Exercise problems in FSM

    Hi , any one knows william fletcher or any other solved examples material avilable in this forum.
  14. V

    FIFO Depth Calculation

    fifo size calculation The logic is very simple. I will expalin it in a non technical way. Suppose there is a person A and B. Now A can throw 10 mangoes at an instant of time. But B can catch only 6 mangoes at the same amount of time(remember this is very important i.e the phrase same amount of...
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    How to calculate the depth of FIFO and what are the designs contraints for it?

    fifo interview question hi, anyone can provide good material on FIFO,implementation details amd Application point of view. Thanks
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