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Recent content by vikas_lakhanpal27

  1. V

    How to code VCS coverage analysis report?

    cmview vcs -cm_exclude I am using Cmview and coverage file i have dumped wid VCS.
  2. V

    How to code VCS coverage analysis report?

    i have dumped testcase*.line , testcase*.fsm, and testcase*.tog while doing simulation. How can I do code coverage analysis now? Can anyone help? regards, vikas
  3. V

    Can anyone clear my synthsis doubt?

    wire load model top segmented I am confused with set_wire_load_model a>top b>enclosed c>segmented. Can anyone explain these in detail? And also what is set_wire_lode_mode ? how both are diffrent?
  4. V

    how metastability does not occur in Async Fifo

    metastability clock domain Async fifo supports 2 independent clock for data read and write(write happens on write clcok and read happens on read clcok) . So there is no chance of metstability.
  5. V

    Why do we avoid latches in the design?

    Re: Latches in th design Whenever latch is enabled it will pass watever is there on its D inputs to Q output. If suppose any glitch is coming on D and latched is enabled it will pass it to q. Glitch always create problem u would be knowing this. Latches are fast,consumes less power, less area...
  6. V

    The question about DC synthesis!

    i went through the whole discussion on this topic and was not able to find wat is the problem if reset is coming in data-path? if it is design specific problem then i dont know but else i am not seeing any probs reset coming in data path. Anyway I think if we should give ultra_optimization to...
  7. V

    how to check or condition in ifdef?

    or condition in ifdef Can anyone tell me how to check or condition in Ifdef statement? I am trying `ifdef (a || b) but it is not working?
  8. V

    combinatorial ckt in clock path

    i think parmod is right that glistces can occur regarding skew we can take care while doing CTS. Anyways some skew still will be there after CTS on the basis of diffrent PVT but that we can model in Gate level simulations and STaA
  9. V

    what is the present situation of semiconductor industry

    Dont worru pramod.It still good in India.Amd is laying off buut all abroad not in India.. Dont worry dear friend if we have capablility semiconductor still is ok...
  10. V

    Verilog doubts about sensitivity list code

    Verilog doubts Hi parmod, thanks for the reply.I agreed that it is acceptable but is it a good design practice?
  11. V

    Unmapped point when doing LEC

    lec unmapped points have u given ur falttening options properly? try this command at the set system mode lec -nomap map key points comapre -seq_constant -seq_constant_feedback -repeat map key ponits. Might be it help u but u shuld find why it happening.
  12. V

    Verilog doubts about sensitivity list code

    Verilog doubts In two years of my exp in VLSI industry first time I saw a code in verilog in which senstivity list looks like always @(posedge clk or negedge rst or negedge pwrfail) I am trying to see how will Dc synthsize it. In between wat u ppl think is it good way to write code? And...
  13. V

    Why do we use antenna diodes?

    Why do we use ANTEnna diodes? In an IP's RTL I am seeing that all the inputs are going to antenna diode.The anteenna diode doesnot have any output either.Why are we doing like this.can anyone please help me?
  14. V

    What Should be the Synthesis circuit

    Flop. The process or always block which works on posedge or negedge of a clock takes flop. Also in ur case a is always assigned to '1' the synthsizer can simply tie a to '1'.Why to unnecessarily use a FLOP? Right?
  15. V

    STA tool and multi-cycle paths

    STA doubt Thanks!
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