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Read this book, for better idea.
J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Pearson Education, 2003. [abstract]
First find the ICC user guide, to help you with commands.
1. Create Milkyway with tech file
2. read verilog
3. read sdc
4. set tlu
5. set_delay_calculation
6. derive_pg_connection
7. initialize_floorplan
8. create_rectangular_rings
9. create floorplan strategy using set_fp_placement_strategy...
The best way is to have a layout strategy to reduce Area. Use ICC to do that. Also you can do design partitioning to optimize on area. THese are all suggestion. You need to decide on them.
DC just converts your rtl to gatelevel. To reduce the number of cells in your gate level netlist you will have to play with constraints or how the design has been coded. In simple terms, larger number of gates in the gate level netlist, larger the area and power.
ICC on the other hand takes...
There are tons of approaches to layout that can reduce area and power. One is making sure you have your standard cells that connect to a certain port close to the port.
priyanka , you need to some experimentation with the commands.
to reduce area, use optimize placement of standard cells to match the ports, but this might increase the power. I am not sure about what you mean time?
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set_fp_placement_strategy -congestion_effort medium...
Hello bsrin,
I know hercules generates the Milkyway database for doing both DRC and LVS. I personally have not setup hercules, but have always run a run_script for it in analog world. I have no idea of all the things you have mentioned as I am a digital engineer.
-V
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DC topo can read the def file . You can use DC-topo with either ICC or SOC encounter. I usually prefer ICC as it can read Milkyway database generated by dc-topo easily.
Hi bsrin,
Milkyway database consists of a directory of LIB and FRAM folders. There are additional folders created for errors or db files. These folders consist of synopsys binary format databases. That answers 1 and 2.
I am not sure on 3. But on 4, the answer is no. Calibre is a tool that...
I think the library that you are using is a smic 180nm ( smic18_10wl) not TSMC. For synthesis, just let the tool select a default one, unless you are using Design Compiler -topographical( Please check the website of Synopsys for topographical) which needs different files called the tluPlus(...
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