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Hello Experts,
I am using Altium 10. If I click a component in Altium 10 it actually select (white area) as in Image B. But actually I want to select like " Image A". But my current setting is not give the selection like Image A. Please help me.
Note : Due to extra area selection as...
Re: Spartan 3 RAM
I am need to interface a CCD for xray imaging with FPGA. So I require a CCD driver chip and a 12 ADC converter. After that can take the digital signals to the FPGA.
Could any one suggest me a chip which hold the driver and a 12 bit ADC in one.
I have a CCD sensor which...
Has any done the interfacing between two MACs using RGMII. If so could to tell me how to do the connection. I hope Tx to Rx data to be connected. I have doubt on the Clocks and control signals.
Thank you,
Vijay
Re: FPGA to PCB
UCF is the file you have to use, this file has the pin information that you have assigned during synthesis on the xilinx tool. Whether my answer is helpful
with regards,
Vijay
Hi,
If I am not using my JTAG mode of my processor how to handle it.
If I put a pull down in TRST pin alone and the remaining JTAG signals are left open. Will it be fine or do I need to put pull up tms and tdi also ?
Thank you,
VJ
PCI Express Material
Dear All,
Could you please share the documents on interfacing the PCI express 1X , 4X.
which has the explanation on each pin in the PCI express finger.
With Regards,
Vijay
basics of hardware designing
You need to narrow your domain in which way you are going to do hardware design, There are some domains like Hardware Board design, PCB Design, Power supply design, RF design etc, Choose a domain depends on your interest. Then start learning and ask questions in...
Re: HDLC-IP
it is not working properly..
In Open cores hdlc code... last byte is getting repeated in the transmission that to for 7 bits ..
In the Project post.. Test bench data is woring fine.. If i transmit 0xFF, 0 xFF, 0x01, 0x00 then the result is 0xFF, 0xFF, 0x00, 0x00.
Any one have faced...
Dear All,
I have seen this in a C file .. I need to implement this in FPGA... Actually it is a CRC-16 generator and unsigned char crc_arr[6]={0xff, 0xff, 0x01, 0x03}; is the test data input for the generator. Actually there are some defined values in fcstab[256]. I cannot save all the values...
Hi,
We have a processor which can support SS7 signaling and
I have captured some packets from the processor and following are the details
First packet FF FF 01 03 BC D4
second packet FF FF 01 00 27 E6
BC D4 are the CRC -16 field in the first packet and
27 E6 are the...
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