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Recent content by vijayaganesh

  1. V

    Preventing antenna effect in IC layout design

    thanks erikl and dick_freebird.i jst got it.but i hav little doubt in that ..plz clarifies me.still now i m thinking every layers in cmos can happen step by step procedure during fab, so i know the process .my doubt is first m1 then m2 them m3.....like this process only the layers got deposited...
  2. V

    reactive ion etching

    ya i m clear now thank u everyone!
  3. V

    Preventing antenna effect in IC layout design

    that ....my question is ....does the reactive ion etching process happens on implant of every layers (i.e.poly diff,well,m1,m2.....etc)?
  4. V

    reactive ion etching

    well i got it now,but how u say that voltage does not cause any damage to junction?
  5. V

    Preventing antenna effect in IC layout design

    Re: Antenna Effect i go through this thread and come to know that reactive ion etching process takes place in every metal layer formation on die.is it correct there is m1 ion etching m2 ion etching,...etc will happen?
  6. V

    reactive ion etching

    why reactive ion etching is necessary for fabrication process.....?and anyone clearly tell me how it cause antenna violation?
  7. V

    NTAPS and PTAPS and its necessary?

    thank u its really helpful ur reply clearly explains everything
  8. V

    NTAPS and PTAPS and its necessary?

    can u please explain in detail or please explain with any pictures?because i am preparing for an interview and i hav to clear this....so will u do it please
  9. V

    NTAPS and PTAPS and its necessary?

    Can anyone explain clearly how NTAPS and PTAPS can solve the latchup effect by fabrication point of view? And one more thing its the only job for PTAPS and NTAPS
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