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cadence virtuoso IC 6.1.6 is the tool I am working with. I have .csv file containing the eye diagram values. I need to plot. That's all. If there is a way let me know
Hi all,
I have calculated the deterministic jitter through eye diagram in cadence. However, I need my eye diagram to be plotted to matlab. I checked for some inbuilt fucntions for plotting eye diagram, and I found out a command called "eyediagram()" to plot it. But right now I have my eye...
Hi erikl,
I can't use a verilog PRBS within cadence. Is there any way i could change some settings within PRBS instance in Cadence, so that i could get a signal like the one which I have mentioned above.
Hi all,
I need to run a PRBS signal of the form
freq=64GHz, period = 15.625ps
For obtaining this kind of signal, I tried a circuit which looks like the one below
And the parameters for the prbs V6 is as follows:
And the parameters for the prbs V31 is as follows:
But the output signal...
Hi dick_freebird,
I understand your point. But still my question hasn't been fully answered. Though I need inductances to increase the bandwidth of my circuitry, I couldn't eliminate them. Introducing capacitances between the Vbias and vee doesn't make any big difference. However I tried...
Hello all,
I have designed my Clock regeneration circuit in cadence Virtuoso 0.6.1. However, while I was trying to calculate the jitter of the circuitry, there was a bit overshoot and ringing in my circuitry, which I obviously needed to reduce. I need to introduce only capacitors from my bias...
Hello all,
I have created an inductor (3-port center tapped GND one) with a value 240pH. Now I need to make a LVS check for my inductor design. For that I have replaced the ports in my Inductor layout design to labels. However when I try to do LVS check for my inductor design, I am getting...
Hi,
what I meant was, I have already made the layout sonnections for the voutn (of EF) to the vinn (of DA). What I need to connect is voutp (of EF) to vinp (of DA). However, I find making this connection difficult, why because the connection has to pass through the already made connection...
Hello all,
I have some queries regarding the layout design for a complex circuit design. I have to design a cascaded pair of emitter follower (EF) and differential amplifier (DA) circuit blocks, where the outputs (both +ve as well as -ve) of the former block have to be connected to the...
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