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Recent content by verilog_work_group

  1. V

    Xilinx simulator errors: port size does not match connection size

    # ** Warning: (vsim-3015) C:/Xilinx/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'. # Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i...
  2. V

    How to start DSP FPGA design? What tool can be used?

    DSP FPGA Design How to start DSP FPGA design? what tool can be used?
  3. V

    How to learn PERL script

    how to learn perl script CAN ANYBODY TELL ME THE SOURCE TO LEARN PERL SCRIPT.
  4. V

    Design without verification

    Is that possible to design witout using modelSim?
  5. V

    What are the features of DCM in comparison with BUFG?

    What is the feature of DCM compare to BUFG?
  6. V

    Perl Script or TCL script

    Which language is better to learn in verification ...perl or TCL? All replies without rational argumentations will be deleted.
  7. V

    What is duplication register?

    What is duplicated register?
  8. V

    Anybody can share Xilinx Training documents?

    advanced xilinx fpga design with ise Can anybody share xilinx training documents here?
  9. V

    What is different between BUFG and IBUFG

    ibufg bufg What is major different BUFG and IBUFG?
  10. V

    Effective learning the synthesis method

    Can you guys recommend how to use synthesis tools effectively?
  11. V

    What is advantage of microblaze?

    microblaze advantage What is advantage of microblaze? is it hard to use?
  12. V

    Most effective verilog verification method

    Is there any effective verilog verification method? How good to use systemVerilog?
  13. V

    Which synthesis tool is better: XST, Synplify Pro or Precision?

    Which synthesis tool is better ? XST, synplify pro, precision??
  14. V

    What is different between PLL and DCM?

    dcm and pll How to differentiate PLL and DCM?
  15. V

    Verilog Verification Method

    How to learn Verilog Verification Methodology? Any good book?
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