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Recent content by venkatec

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    techniques to save power when using DDR3 memory - ideas

    Hi Memory is always required ,when a system is on and you are working with it. But when ever you keep your system idle ,you no need to have contact with memory +controller so in that time you can switch off the power consumed by the controller + mem using isolation cells in your design ...
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    [SOLVED] ddr3 memory controller

    Hi i think you can refer a chip name called dm365 ddr2/mddr guide, in google you find more info on it.. Venkat.k
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    Required Circuit to convert Square wave from 5v to 12v

    use linear regulator/ converters from dc-dc. u can google this...
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    VHDL Syntax error in Modelsim simulator

    Re: VHDL Syntax error Hi, I Sloved this problem. in this code bug is here.. parallel_data(count-1) <= serial_data_in; Here count is range from 0 to 55 so i am doing count-1 operation that means 0 -1 = -1 -1 is not in the range of count.SO that is why simulator is strucked at this...
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    VHDL Syntax error in Modelsim simulator

    VHDL Syntax error Hi frnd, Here is one small issue while simulating below code signal parallel_data:std_logic_vector(55 downto 0):= "00000000000000000000000000000000000000000000000000000000"; process( clock,reset) variable count: integer range 0 to 56 := 0; begin if clock'event and clock =...
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    VHDL Syntax error in Modelsim simulator

    Re: VHDL Syntax error Hi Frnd, The problem is sloved. Thanks. vk
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    VHDL Syntax error in Modelsim simulator

    syntax error in vhdl Thanks for your kind response. I am trying to find correlation of two sequences ,for that i am using one IEEE derived fromula.. Yeah "fo" is std logic vector,So i am using the libraries you mentioned. I will try with your solution and get back to you... Thanks...
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    VHDL Syntax error in Modelsim simulator

    Hi Frnds, Below vhdl statment is giving syntax error in modelsim simulator,Could you correct this error. f0 <= ((seq_pat(0) xnor Rx_data(55))+(seq_pat(1) xnor Rx_data(54))+ (seq_pat(2) xnor Rx_data(53))+(seq_pat(3) xnor Rx_data(52))); error:** Error: D/binary_pattern_correlator.vhd(74): No...
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    How to generate random number between 44 to 55 ?

    Hi Frnd, I tryed to use the syntax you have given but its printing different values which are in not range code follows here ----------- module test(); reg a; reg b; reg c; wire out; reg[7] range; always repeat(24) begin #100 a = 1'b1; b = 1'b1...
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    How to generate random number between 44 to 55 ?

    Thanks for your responses, How to genrate random no between any range(Ex:Take some rane 55 to 71) using $random command in verilog.
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    How to generate random number between 44 to 55 ?

    how to generate random numbers between 1 and 55 Hi Dear Frnds, How to generate random number between 44 to 55 in verilog or VHDL?
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    [SOLVED] The Best vlsi system design course in KCS-bangalore.

    kcs bangalore This program covers the entire flow of VLSI System Design. This KCS Certified Course offers in-depth hands on training on VLSI Design and verification methodology. Students at KCS(KANT get real time exposure on complete range of EDA tools. These 3-4 months training will leapfrog...
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    good vlsi institutes in bangalore

    best vlsi institues in blore Hi Frnds, Kcs(KANTA consultancy services) company is the best for this course in bangalore.This course is instructed by MNC experts.I think ppl who are seeking career in Vlsi System design should go for this course to get good industry exposure...
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