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Recent content by vashistha

  1. V

    PODE and CPODE layers in tsmc

    What is the use of PODE and CPODE layers in tsmc 16nm technology. Does these layers get fabricated or not.
  2. V

    dummy in the layout of finfets

    Why we use dummy gates in the layout of finfets?
  3. V

    flip in cadence virtuoso layout

    How to use flip command in cadence virtuoso layout editor. When i am using flip vertical command and then run drc it will give so many errors and offgrid errors and before flip drc is clean.
  4. V

    error in op amp layout if using pads

    it is a post layout simulation and power cosumption is between 500 uW to 1 mW - - - Updated - - - yes...netlist is correct. when i do a post layout simulation without using input pads the result is correct
  5. V

    error in op amp layout if using pads

    i am working on the layout of opeartional amplifier it gives the correct output but when i make pads for input, output and power and connect inputs, output and power to their respective pads the gain decreases by 20 dB. Pads consists only of square made of metal layers. If i increases the width...
  6. V

    Difference in pre and post layout simulation

    I am working on the layout design of reference current circuit. The simulation result from schematic are 10 uA for both nmos & pmos but when i do the post layout simulation the output is 8.78 uA for nmos & 6.96 uA for pmos. Please suggest me how to optimize my layout so that pre & post layout...
  7. V

    Layout of capacitors

    Yes...i mean drawing a cap array. I am using Cadence Virtuoso Layout suite L.
  8. V

    Layout of capacitors

    Hii, Thanks for your reply @klausST but i think the layout is software independent. I just want to know the basic principle of drawing layout using unit cells
  9. V

    Layout of capacitors

    Hii, How to draw layout of capacitor using array. Thanks
  10. V

    standard cell library

    Hi Prashanthanilm, I dont understand what are you trying to explain. Can u Please make it more clear. Thanks
  11. V

    ac noise analysis using hspice

    I am doing noise analysis of op amp using hspice. The value of inosie, outnoise , flicker noise and thermal noise obtained from analysis is zero. Why??
  12. V

    manual for virtuoso layout XL & GXL

    I need a manual for Virtuoso Layout XL & GXL.Please provide a link. Thanks
  13. V

    lvs error for resistor

    i am using unsalicided pplus resistor, it has three terminals (plus minus sub). How i make the sub terminal in layout.Is sub terminal connected to ground
  14. V

    lvs error for resistor

    i am using calibre
  15. V

    lvs error for resistor

    I have to make a layout of 200k resistor so i connected 20 resistors in series,10k each. But when i done lvs it will give a property error. PROPERTY ERRORS DISC# LAYOUT SOURCE ERROR 1 0(1.055,0.705) r18 R m: 1...
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