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Recent content by vasaroopak

  1. V

    Need help to understand spice statement

    Hi All, I am hard time to understand below spice statement. .measure AC cap_acc find par('-1*II(VGA)/(vac*hertz*2*3.14)') AT=100000hertz Can anyone help ? Thank you.
  2. V

    For Intrinsic cap calculation, what should be the time interval for integration of current

    For Intrinsic cap calculation what should be time interval for integration of current Hi All, I am trying to get VDD cap of SRAM memory macro. I am ramping VDD by 50mv in a specific time interval and then integrating the I(VDD) for the same time interval. For different time intervals like...
  3. V

    How to measure current probed by isub() command

    Hello All, I am trying to find leakage of different instances/subckts using spectre xps. I tried using chk1 dyn_subcktpwr inst= port= depth=4 time_window=[36n 37n] It dumped an empty xml file. Then moved ahead with spice commands as under: For .probe i(vvdd) .probe...
  4. V

    List of latches used in netlist?

    List of latches used in netlist ? Hi All, Any way to extract a list containing all the latches used in a netlist (Sram macro) ? Does any simulator support this kind of functionality ? Thanks, Roopak
  5. V

    Significance of following Spectre XPS options ?

    Hi All, i tried search in spectre documentation but could'nt find below options. 1) .options sim_opt_macrotable_ignore_rg=1 2) .options sim_opt_macrotable_termcurscharge=0 3) ModOptions options redefinedparams=warning 4) parameters pre_layout_sw=1 I think it...
  6. V

    Force spice measure statement

    For statements as under .meas tran find_max param='max(meas1,meas2,meas3)' if the value of meas3=NaN then the value of above measure statment (find_max) will also come NaN. Any way to force spectre to find the max among the available values ? Thanks, Roopak
  7. V

    Node name used in .measure statement

    Consider the following meas statement. .meas tran c2c_read_to_write_blrst_min min v(SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\xxl_blx4/xblx10/xp5/mp0.g ) from=cycle1_start to=cycle1_end .meas tran c2c_read_to_write_blrst_min min v(SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\BLRST )...
  8. V

    Is verilog view required for nelisting ?

    Hi all, I am netlisting sram cell using block level subsircuits. Will it require verilog models ? If yes then please give reason. Thanks and regards, Roopak
  9. V

    Worst and best PVTs for memory compilers

    Hello all, I would like to discuss the worst and best Pvts for timing, leakage, dynamic power and capacitance. Also if we can discuss the best and worst extraction for the same. I basically work in memory ips like sram. thanks you
  10. V

    How to extract the cap of a nmos transistor using ELDO ?

    Hello all, I want to extract cap of a nmos transistor using eldo. Following are the contents of .cir .INCLUDE "minNminP" XMM20 0 dbl 0 0 NHVTLP W=6.0 L=1 NFING=1 NUMBER=1 STYLELAYOUT=0 NGCON=1 Vdbl dbl 0 1 .option nomod .option captab .op .dc *.tran 0 1n .END But I am getting cap value 0...
  11. V

    Difference between extraction strategy and extraction methodology ?

    Hello, there are extraction methodology like CC, Rc etc and extraction strategy like RCMax Cmin Cmac So whats the difference between them ? How is the extracted capacitance effected by them ? Thanks and regards, Roopak
  12. V

    requirements for layout design

    yes they are included in the lite version
  13. V

    requirements for layout design

    generic rule files are included in the software
  14. V

    requirements for layout design

    yes it has a lite version which is free
  15. V

    Looking for open source RTL to GDS flow training

    https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CDAQFjAA&url=http%3A%2F%2Fuserwww.sfsu.edu%2Fnecrc%2Ffiles%2Fsynopsys%2520tutorials%2FASIC%2520Design%2520Flow%2520Tutorial.pdf&ei=IAcZUeeIDImJrAfPqYDYAg&usg=AFQjCNEWXCxcwBglKa2N7DGghcNuAKSlnw&sig2=ql3VRfdLWx_gGkzyxPNt...
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