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Recent content by varunvats69

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    Questions about a for loop in a sub-module of a SHA 256 processor

    Hey all, I'm using a for loop in a sub-module of the SHA256 processor I'm designing. I haven't synthesized it yet but intend to do it very soon. Before going ahead I thought it worthwhile to get an idea of the hardware the synthesis tool will generate. I'm using Synopsys Design Compiler to...
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    Help with Verilog simulation

    simulation for inout in verilog Hi, I designed a 2 to 1 Mux using a bufif1 and a bufif0 (file attached). The simulation results (wave.jpg) show that the output OUT goes into unknown state x at two instances, one at the beginning and another when S (ctrl input) transitions to 1 from 0. Can...
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    Race condition check in Verilog

    non blocking verilog race Hi Gharuda, This is something interesting you've brought up; it has been gnawing at the back of my mind for quite some time. I am a Verilog novice and had uptill now assumed that as long as you didn't insert a delay between assigning values to variables, they would be...
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    Race condition check in Verilog

    verilog rs latch Hi, Is there a way to check for race conditions in Verilog? For e.g., I implement an RS latch using nand gates. The situation in which both the inputs are 0, the outputs q and qbar both will be 1, which is a violation of the definition of a latch. Does Verilog point out such...
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    bit combinations in a byte

    2^8 = 256.
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    Cause of Metastability and It's Solution for it's Removal

    Re: Cause of Metastability and It's Solution for it's Remova 1) Possible causes of metastability: i. Slow transition times (rise and fall times) at the input of devices, which could in turn possibly be due to a low VDD, high parasitic capacitance and cross-talk. Also do check the formula...
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    How to P&R a design using custom cells in Cadence Encout

    Re: How to P&R a design using custom cells in Cadence En I am not sure if tools that characterize custom cells exist, but I guess its a very hectic process when done manually. You need to change a lot of parameters (PVTs) and see how the cell reacts to them etc. Will let you know if I get any...
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    Problems in adding power stripes to power domains

    power stripe Hi, You could probably check the following: 1. While adding stripes, check what you have selected in the Stripe Boundary section of the form. I think it should be Core ring, am not sure though. 2. As for the hard macro which seems to prevent the generation of stripes in some area...
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    please help, how to retrieve layout data in virtuoso?

    Hey can't you just use a file recovery software to retrieve your deleted files??
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    Effect of Oversoot and Undershoot

    I can see atleast two effects of overshoots and undershoots: 1. An overshoot in the VDD or an undershoot in the GND will basically cause higher amount of current to flow between VDD and GND => device burnout possible due to latch-up. 2. Higher current between VDD and GND also means higher IR...
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    Electromigration Fixing in Magma

    electromigration fixing You could use double width to overcome electro-migration issues but I'm not sure if doubling the space would be of help to achieve that though it would help in reducing XTalk. Same with shielding too; it may help better XTalk but not EM.
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    How to P&R a design using custom cells in Cadence Encout

    set_dont_use cadence Hi, Let's start with a design which is currently in the RTL stage and needs to be P&R'ed. The steps to use custom cells in your design would likely be: 1. Create a library containing your custom cells. Remember you need to create two types of libraries- a logical...
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    verilog rokie, any help appreciated

    Thanks a lot guys its workin! :D
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    verilog rokie, any help appreciated

    Thanks a lot mytechface and haneet. Will try what u have suggested. So by default a reg variable is 1 bit wide, am I right?
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    verilog rokie, any help appreciated

    Hi all, I'm a novice Verliog programmer. just started out with Palnitkar's Verilog HDL n I'm stuck up with this very basic program in the exercise of the book. Q: What would be the output of the following? latch=4'd12; $display ("The current value of latch= %b\n", latch); Since this...
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