Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by vaibhavar

  1. V

    ring oscillator design problem

    Hi.. The values seem to be correct. I think you need to increase the number of stages, so that sine wave is properly shaped in to square wave. Right now, what frequency are you getting? Best Regards Vaibhav
  2. V

    Need help in designing high voltage (25-50V) driver

    Thank you for the prompt replies. I am using a process with HV FETs and I dont want to use external discrete components. Frankly speaking, I have not finalized specs. Can you please suggest some specs. My idea is to design a circuit that uses HV tech., which can drive (say) 5-10 standard...
  3. V

    Need help in designing high voltage (25-50V) driver

    Hi, I want to design a high-voltage (~25-50V) driver circuit, which is fully on Silicon. It can be for LCD/LED driver application. Please suggest me some circuits or references. I need some starting point, so any simple circuit will be fine. Thank you in advance Vaibhav
  4. V

    Measuring gm for a differential pair

    constant gm differential voltage Hi, You can find gm in Cadence by using following steps: (1) Perform DCOP analysis, with circuit operating at its bias point. (2) Then go to results>print>DC operating points and then click on the transistor whose gm you want to check. (3) You will get...
  5. V

    replacing an ideal tail current in a differential pair

    Hi, I completely agree with PaloAlto. The dc bias voltage given by u is not able to operate the input transistor in saturation when using current mirror (it will be in cut-off). You need to increase Vdc to get proper circuit operation. Regarding your next question, the ratio (W/L) will...
  6. V

    Transmission line model for twisted pair cable/backplane

    twisted pair transmission line Dear all, I need a transmission line model for twisted pair cable or a backplane trace (differential) for typical lengths, which i can use to simultate with my designed I/O transmitter circuit. Any help/guidance is appreciated...
  7. V

    current mode and voltage mode ckt

    Hi DZC, can u please attach the first 2 books you mentioned or some pointer to where i can find them... thanks in advance Vaibhav
  8. V

    some electronics related ques...help plz...

    1) Transfer Function = GH/(1 + GH) = Av / ( s^2 + 2*(zeta)*(Wn)*s + (Wn)^2) which gives natural frequency (Wn) = sqrt (10) = 3.16 Rest all answers are as given by rwiggins... Regards Vaibhav
  9. V

    LVDS transmitter problem

    Hi Warlike, wat i have understood is that u have fluctuations on Vos & Vod during switching. If that is the case, CMFB circuit cannot be designed with that high bandwidth to filter out these fluctuations (according to my understanding). I am designing a similar circuit with 2 NMOS & 2 PMOS...

Part and Inventory Search

Back
Top