Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vahid_roostaie

  1. V

    Clock gating of the registers banks in a design

    I want to gate the clock of the register banks of my design. as you may know there is an option named:sequential_cell in the set_clock_gating_style command. i don't want to use "latch" as sequential cell, but because some of the top level inputs of the design influence on so many register banks...
  2. V

    generation of .sp fileformat in Design Compiler

    readlef I want to make a cdump file from GSDII to use in soc encounter. as you may know for generating GDSII layout in soc encounter we need Cdump file and cdump file is generated from every standard cell GDSII file.
  3. V

    How to convert lib file to db file?

    I want to construct db file from lib file. is there any special command or special method for this?
  4. V

    power estimation by primepower

    I want to use primepower for power estimation. I've done post synthesis simulation and generated VCD file correctly.then I used primepower commands for power estimation based on it't tutorial. but all the results of estimation are wrong because primepower consider a default 1Ghz clock not my...
  5. V

    problem with two clocks

    Hi! I have to seperated asynchronous clocks in my design.both of them are input ports that have their own registers in my design.I used approperiate synchronizers and the other needed techniques in clock boundary and have no problem in design. but my problem is defining and using DC commands...
  6. V

    How to define two separate asynchronous clocks in a design?

    I have two seperated asynchronous clocks in my design.I used synchronizers and the other needed techniques for these two clocks boundary and don't have any problem in design. I just want to know how can I define these two clocks. with two seperated create_clock commands?. I want to use...
  7. V

    set_case_analysis problem

    set_case_analysis Hi! I haved Muxed two clocks in my design.both of them are coming from input ports. the selet signal of the mux is generated by a controller that works with CLK1 in an special state and the output of clock MUX is a clock that is used in another seprated controller that drive...
  8. V

    How should I define a clock at the output of MUX?

    muxed clock not working I have used set_case_analysis with "get_pins" because the mux select signal is generated internaly is this way ok?but when I want to specify the mux select signal input DC can't find that I found the mux select signal from the verilog netlist file after analyze and...
  9. V

    How should I define a clock at the output of MUX?

    Hi! I have Muxed clocks in my design.there is no relationship between these two clocks I used create_clock to define the two clocks and I want to know that: how should I define the clock at the output of the MUX should I use create_clock for this pin or create_generated_clock? what about MUX...
See more

Part and Inventory Search

Back
Top