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pipeline adc basics
i have some questions about pipeline adc design.
-i want to understand the basics of the digital error correction. how decreasing the interstage gain by 1/2 and bit overlaping corrects the errors caused by the sub-adc.
-why the referans voltages of the sub-adc are +vref/4...
in pipeline design for ex: Does 10 Ms/s means that the clock signal will be 10 MHz??
And what is differantial input? How can be applied a differantial signal to the input of the adc? For ex: a ramp function is applied to the positive input, than what will be applied to the negative input...
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