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Actually I am already using a DCM and the (clock) here is actually an output from the DCM. The entire synthesis has a lot of operations which use that clock.
In the code, I need just one operation, in this case, "b_out <= a_in" to happen at half the clock frequency.
Hi there...
How do I divide the clock frequency by 2 for a simple VHDL code?
For eg. if the code is something like this:
process(clock)
begin
if rising_edge(clock) then
b_out <= a_in;
end if;
end process;
Now if I want the same operation to take place, not at every...
Hi there!
I wrote two programs in VHDL, one to generate a PRBS sequence and another to generate a square signal of 100 Mhz. For both these signals I took the output at the SMA port on the FPGA board (Xilinx SP601). Now I want to multiply these two signals and get the output again at the SMA...
Hmmm Ok!! I wrote a VHDL program to generate an MLS signal using an FPGA (Xilinx SP601 board). I used a clock of 100 Mhz and I took the output from the SMA connector. Now I fed the output to the oscilloscope and got the required sequence as expected. Then I used the FFT function on the Scope but...
Hi there!
Could someone kindly help me out with the matlab code for finding the frequency spectrum of a pseudo random signal. I've saved the data in CSV format from the Oscilloscope (I've attached the file) and I now need the FFT! I did go through similar posts but the method explained is...
I did figure it out by then actually! Thanks a lot mate! I really appreciate it!
The code I used:
process(clk)
variable counter: integer range 0 to 9 :=0;
begin
if rising_edge(clk) then
counter := counter + 1;
if counter = 9 then
Sig_A <= Sig_B;
end if;
end if...
How do I write a signal in VHDL such that Sig_A <= Sig_B is within a clocked process and it is written at every 10th clock period if the clock frequency is say 100 Mhz?
Well I was initially trying to get the output at 100 MHz. I changed it to 20 MHz but the result is still the same. I'm getting a High DC line. Thats all!:sad:
I had previously written a similar code for generation of a normal PRBS using D flip flops. I implemented the LED_OUT there without any problem. The code for that one was:
entity mlbs is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR...
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