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Recent content by ukint

  1. U

    AOCV - Advanced On Chip Variation

    Hi, I am looking for some documents in Advanced OCV. Can anyone help with the same? Thanks, Vivek
  2. U

    Why do we fix load and slew violations?

    Thanks for the reply. Can you elaborate more on your reply. I am not able to understand it completely. So are you suggesting that the STA tool doesnot model the max trans and max cap correctly?
  3. U

    Why do we fix load and slew violations?

    Hi, Can someone explain why we have to fix load and slew violations even after the timing is clean? Thanks, Vivek
  4. U

    Physical design engineer jobs in us or uk

    Hi, I am also looking out for the same. Pls let me know if you get any update.
  5. U

    What are the reasons for less via redundancy in a design

    Via Redundancy Hi, We all know that less via redundancy numbers could cause an yield issue. So what are reasons for less via redundancy in a design. Few things I can think of are 1) High Wire Density 2) Average Wire Density etc Can you suggest few more reasons for less via redundancy or any...
  6. U

    Query on Routing Resources

    Hi, Can anyone enlighten on how the routing resources are decided for each technology? For eg for 130nm process we go upto 5 metal level whereas for 65nm we go upto 7lm or more. Is there any data to support this? Thanks, Ukint
  7. U

    Any concern of overlap for VIA1 and contact

    Hi , If you are very doubtful of via1 stacking over cont, then better go ahead and place it in one place and run drc checker. The checker would flag an error if does not support it. But usually via stacking over cont is very much permissible Thanks, Ukint
  8. U

    How is the shifting of CMOS nodes done and how is the node number calculated?

    Re: Any idea? Thanks all for the inputs. It does give me some idea but not very convincing. Even i am trying to find out. i will update if get some solid answers. Thanks once again. Do add if you come across any interesting answers Thanks, Ukint
  9. U

    General layout Guidelines

    Please go through the e-book "Art of Analog Layout" which could be found in the download section to understand the basics and guidelines to be followed for critical analog layouting Thanks, Ukint
  10. U

    Does Layout engineers complete DFM and release the GDS?

    Re: DFM DFM has become critical for designs below 65nm and below. I have worked on 65nm but didnot see specific rules set for DFM. But for 45nm, DFM is very critical and there are checkers which need to be run after the layout is drc clean Thanks, Ukint
  11. U

    Can you explain this?

    Can you help me with the url. I would greatly appreciate that
  12. U

    diode in CMOS technology

    Nowadays, Diode layer is also used. They are used with a tap to differentiate anode and cathode. Cathode is the one with the tap. Regards, ukint
  13. U

    Decoupling capacitor for power supply ?

    Basically MOS capacitors are better. NMOS caps are preferred over PMOS caps due to the presence of large intrinsic capacitance for NWELL when compared to PWELL. Hope this helps! Regards, Vivek
  14. U

    How is the shifting of CMOS nodes done and how is the node number calculated?

    We have seen that the CMOS process is shifting from higher nodes to lower nodes such as 130nm to 90nm and 90nm to 65 nm etc. How is the shifting of nodes done and hows the node number calculated? Why do we have to shift from 90-nm to 65nm and whynot say 75nm. Thanks, Vivek
  15. U

    Can you explain this?

    What will the outcome when the PMOS of inverter is connected to VSS and NMOS is connected to VDD? What would be the difference when compared to the operation of a normal inverter where PMOS is connected to VDD and NMOS connected to VSS Thanks, Ukint
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