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#Spectre #Cadence
I was not able to get the pole frequency from DCop values of a simple circuit. I need to use the DCop values in order to verify my calculations used to govern my design process. This is also kind of required, or at least much welcomed in my thesis. Also knowing from where the...
You have asked the same question at different forums.
https://designers-guide.org/forum/YaBB.pl?num=1589646089
This behaviour is discouraged, since a later reader will have a hard time to follow the sequence of answers or even finding the final solution.
What can one gain of having millions of resistors and caps? The simulation results will be more accurate for sure, but it does not help to answer the question how to modify the layout to improve the performance. To pinpoint the main cause of the degradation of circuit performance you have to...
Without matching your devices might not behave the same. It is important where you rely on exact ratios, which is everywhere in analog design.
You can look at almost every circuit design book, lecture notes. There are plenty on the web I am sure.
I said, that it is not always necessary. If the cross coupled transistors of a VCO have parasitic cap, then it is not the end of the word, it just means that it will participate to your tank capacitance.
An inductor is also just a trace, but you do not have walls around it. If you want to...
You can always add a cap into your schematic and simulate its effect. In the case of an RF VCO it is tolerable (the tank cap will be a bit higher), so even in RF there is no hard rules for that.
In the kHz regime you can forgot the capacitances, but make sure you are there. In a diff pair you...
100uA with 200mV over the threshold gives 0.5...1mS. I will use the last one. Using 1pF cap you can get 160MHz 3dB bandwidth. To reach say 160kHz, you need 1nF. It is hard to integrate. Not to mention the gate leakage of the cap! It can deteriorate the mirror performance.
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Re: how we remove these off grid errors in 45 nm Technology
I suppose you should move it back to the grid.
Also you should look up how to write a question in forums. You won't get too much answers.
My best guess is a series resistance at the source of a common source stage, or significant I*R drop where you set the voltage difference for the N & PMOS gates.
This is a typical example where you have to find it. Freebird's suggestion is the usual way. Most designers have a feeling what...
The main point behind simulating all corners is to pinpoint critical circumstances for the circuits. With other words: if your circuit passes all the extreme corners then people will be more confident that it will work.
There is nothing like input and output referred noise if you short the input and the output. Let's assume that we have some noise injected after the gm stage before the feedback. Control (feedback?/signal flow? - don't know its exact name) theory tell us that this noise will be reduced by the...
Yeah, sure! There are freelance layout engineers who would do the job for a nice sum.
Come on! Just do the homework! If you want to be an IC design engineer than you have to learn how to do a layout by your own.
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