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spef sdf pt
Hi, need your help.
When PT write SDF file,
If we have same spef file, same library,
but we set different clock uncertaince, do we get same SDF file?
I want to know, if we set different clock uncertaince, the timing check of DFF will be different or not.
Thank.
ECO
No, You need to evaluate your situation and current stage, If there are many violation in your after CTS netlist, it's need tools to fix the violaiton.
No need for quit, just reading some book, but in my experience, you 'd better to learn the basic CMOS circuit, it help you to design the hight performance circuit.
1． We consider the 4bit situation and get the truth table
Define,
Input datain [3:0];
Output P2nd [1:0]; //If exist second 1, the position of second 1
Output P1st [1:0]; // the position of first 1
Output exist; //Second 1 exist
Output only1; //Only 1 exist
Truth table...
Your SPEC maybe
1. Input 32 bit data
2. Detect if there exist second "1" bit
? 3. Detect the position of second "1" bit
If the timing not very tight, your could use a CSA array to detect it. If the Sum of all 32 bit > 1, then ther must exist second "1" bit.
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