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Dear kishornakul
Thank you for your reply.
I am not familiar with Design Compiler setting but The Design Compiler was installed on linux server long time ago
and I access and run it using my user from a Window7 PC via putty.
It seems that the design compiler will run on server rather than on my...
Dear friends
I am from Japan.
I am trying to use design compiler installed on server in my institute.
However, when I starting up design compiler by running command:
..../synopsys/Synthesis/current/bin/dc_shell-xg-t
on the server, a message said that
Fatal: Design Compiler is not enabled...
I would like to run the mc8051 core supported by Oregano System with my external instruction and data memories in Verilog but the simulation runs and gives INCORRECT result at the "Post-Route" simulation event the "Behavioral" simulation gives the correct result.
(The simulation for vhdl...
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