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The transmission line dimensions appear to be fine, so your problem is likely a result of the mismatch at the connectors due to the narrow gap between the ground flood and the large center conductor of the (SMA?) connectors. If the center conductor is a thru-hole type, the same concern may be...
In order for the Height DRC to work, the components on the board need to have height information embedded in the footprint. This is defined through either the presence of a 3D body, or by the component height value entered in the component properties (for use when no 3D body is present)...
You can create a panelized array in Altium, but as Klaus recommended, it is usually easier to have the PCB manufacturer panelize it for you. That way they can optimize the array for their tooling, processes, and panel size. You may wish to specify how they are attached (mouse bites, v-groove...
In the PCB editor, you can add nets to the board using the following menu option:
Design > Netlist > Edit Netlist...
Then click "Add" to create a new net. Once it's been added, it will be in your available netlist when placing objects on the PCB.
Edit: Whoops, double post.
Change the "Pour over same net polygons only" setting to "Pour over all same net objects" under that polygon's settings. (See your second image.)
Also, the polygon clearance from GND shown in the first image looks weird since it appears to only be creating clearances from the trace and not the...
Turning off the "Use Alpha Blending" option should resolve your problem. This is a common problem on several of our workstations.
You can find it under DXP > Preferences > PCB Editor > Display
The schematic sheet numbers are likely incorrect for your project which can result in the output only generating a PDF of a subset of the schematic sheets. While in your schematic, select Tools > Number Schematic Sheets. In the dialog box that pops up, verify that the values in the SheetNumber...
Yes, this can be done in Altium using "Rooms". It allows you to generate one instance of a layout and then quickly duplicate that layout for the additional identical circuit channels. You can also use a traditional copy/paste of the copper/components, but that requires a little more manual...
In general, yes. Any additional process step adds a cost, but based on my experience, the primary cost driver is the number of lamination steps. If you can keep your PCB to a single lamination step, that would be ideal cost wise. If you have to use buried vias, it would be best if those buried...
The two individual "VCC_VD_3V3" power nets are automatically tied together since they are on the same sheet and have the same net name. You do not need a net-tie for this scenario. If you are looking to tie another net with a different name to the VCC_VD_3V3 net, then that would require a...
I don't consider 20 minutes to be a "considerable amount of time" if it helps me identify a process that will potentially save me significant time in the future. I'm using my original solution for now, but I was just curious if anyone else had a better method. There may not be one.
I thought about setting them up as blind vias which would generate a separate drill table as intended. However, if I set them up as blind vias, I'll need to add keepout regions to the layers above or below the via that will be back drilled to ensure that there are no clearance issues during the...
Does Altium support the creation of a separate drill table for back-drilled vias? If not, I figure I could use a unique via size and specify the controlled depth drilling info in the fab notes, but I was hoping that Altium supported it directly. Anyone have any tips or suggested methods...
Based on your schematic and the ECO image, I would guess that the error is due to the lack of a net name for your GND symbol. In other words, your GND symbol has a blank net name. The schematic compiler will accept that and not display any compile errors, but the PCB tool will not.
While in...
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