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Hi, Gurus,
I designed a conventional 1X6 patch antenna for 77GHz, and got the max gain 14.2dB.
I want to increase the gain more than 1dB but with limited length, so I designed an antenna with the following pattern.
The problem is that this pattern also have the max gain 14dB., even I made is 1X8...
Hi, Gurus,
I am simulating a 62G antenna.
For 1X6 patch antenna, the max gain is 14.2dB.
So I increased it to 1X7 patch, and found the max gain is 14.5dB.
The antenna is used as the RX antenna for 62G mmwave, so it's max width is half the wavelength, i.e. less than 2.4mm.
And the length is...
Hi, Yes, I know it.
I am curious about what the functions of the net2 block and the net3 block are.
Does anyone have datasheet for: The U1201 is marked code as "9857-00", Package QFN52. ?
Hi, FvM and Other Gurus,
here is the SCH more precisely.
The U1201 is marked code as "9857-00", Package QFN52.
I searched and found it should be a product of NS, but can't find its datasheet.
May you comment on the NET2 and NET3 function?
Thanks.
Best,
Tony Liu
1709880758
@FvM @D.A.(Tony)Stewart
Attachment is a picture of the board. I can't find the model #. If you need the model #, I will try to find it.
This should be a very old TEK oscilloscope.
Hi, Gurus,
I need to layout a mixer, using the examples in the ADS. The SCH is as the attached picture. The RF is 2.4G.
I want to know whether I should make the circuits symmetry or not.
And the RF phase of A and B points should be in phase strictly or not, and vice versa for C and D.
Best...
Hi, gurus,
I designed a power split from port1 to port2 and port3.
Now I want to calculate their phase difference in deg in Ansys.
So I using this function: cang_deg(S(2,1))-cang_deg(S(3,1)).
I hope the diff should be zero.
But I found someone said that this calculation is not precise. They said...
In the attachment report, it showed the conversion loss when IF=1Hz, 100Hz. How can they do so?
I guess they tested in Radar, but how to calibrate the test system?
Best,
Tony Liu
Hi, Gurus,
I met this mixer circuit, as the following picture.
I have several questions:
1. What is the RFC for?
2. If for matching the input of diodes, why it is in the root of the pin? And the diodes input impedance should be varied by the freq and input LO power level, right?
Best,
Tony Liu
Hi, Gurus,
I designed a LNA 1st stage with CE3520.
Simulation is done, and test results showed 8dB gain with VNA test.
But when I tested NF with 346C noise meter in the spectrum analysis, which has NF function, I got -1 or -2dB NF with 8dB gain.
I checked that no self-osc at the output, which...
Hi, Gurus,
I desgined a LO at about 15G.
Its phase noise is bad @10KHz, but @1K & @100Hz is very good.
I wonder the reason for this case.
Attachement "15G" is the PN of the 15GHz, and there is a peak @10K. In theory, it's alomst about 3dB variation from theory value. My PLL bandwidth is about...
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