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Recent content by Toneski_IP

  1. T

    Clock & Gated Clock -> Clock & Clock Enable

    I think I know what you are trying to do, but if this reply is wrong, please let me know... This is assuming that there is a separate read & write clock to the FIFO. If the clock is gated at the Gameboy end (ie its active whenever there is fresh data) then just use that as the FIFO writeside...
  2. T

    Case statement question

    Succinct answer..... I would have thought it would actually synthesize down to 4 LUTs & 4 FF's Sorry to be pedantic...:lol:
  3. T

    Reciprocal of a std_logic_vector signal.

    The long answer is :- It depends. What resolution do you require the result to be? Are you OK with a rounded integer result? How fast do you need the result? (Single clock, multiple clocks?). Do you have a spare multiplier in your fabric? If you can come back with some answers, then I may have...
  4. T

    strange problem in ML605, using diffectial clock I guess

    My 1st problem with your sample code is that while you don't mention reg[23:0] in your UCF file, you are still outputing these bits. If you dont tell your tools where these connections are to go, the tools will gladly assign them to ANY spare pins you have. And when I say ANY I mean, ANY - I...
  5. T

    help with vhdl coding

    ... or you could replace your process with MUX_OUT <= (others => '0') when RES = '0' else A_In & B_In & C_In & D_In; Your process doesn't specifiy what should occur when EN = '0', so I've omitted that too...
  6. T

    Please suggest some good material on asynch FIFO and CDC

    The Sunburst papers written by Peter Alkfe are really your 1st call on how exactly a FIFO works - he is after all Mr. FIFO. (He held the patents on FIFO design). If you want to calculate how big your FIFO needs to be, you need to determine how fast data is arriving at your FIFO and how fast your...
  7. T

    FPGA LUT delay for a simple function

    Yes - the LUT delay will be constant and defined in the datasheet for your particular logic device. If you imagine your logic being implemented within a small RAM, then you can visualise that as long as your logic function is in a single LUT, the propagation delay will always be constant (it...
  8. T

    i have a problem with this code

    One thing that did strike me with this code is the line " if(onekhz <="1111100111") then --divide by 1000". This line will reset the counter onekhz back to 0 whenever onekhz is less than or equal to "1111100111" - ie, it will hold the value to 0 all the time. Is this what you wanted? I would...
  9. T

    display characters on VGA using verilog

    You are going to need a character set definition store, and some method to determining what you want displayed where. I dont think your CPLD has internal memory (though I may be wrong), but as a (very) rough guide, you are going to need approx 16k bits to store a character set (upper case and...

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