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Hi, All,
We just got a new tape-out. One the same wafer, about 60% failure because of big IDD current. Most of those failure and at the edge of the wafer. We measured the IDD by stepping up the VDD voltage. I-V curve look like a forward biased diode. Could anyone tell me what could be the...
Still ESD issue
Very common ESD structure for an output pin is two diodes, one is connected to VDD, and the other is connected to VSS, both are reverse biased in normal operation.
For this kind of ESD structure, if output pin's voltage is within the range of VDD and VSS, the current through...
Re: ESD design
Hi, ESDSolutions,
Thanks a lot for your quick reply. I'm not in ESD design field. But because of limited resource in my current company. I was asked to try this design. So, some points of ESD design is straight forward for you, but hard for me to understand:
"OK: 18V tolerant...
Re: ESD design
Hi, Mikersia and ESDSolutions
Yes you are right. In this process I have high voltage devices with thick gate oxide. The output device directly connected to the output pin is HV NMOS and HV PMOS. The can sustain 18V.
ESD design
I'm going to design an output driver using a 0.35um tripple-well bicmos process. The supply voltage of this output driver is Vdd=3.3V, and Vss=0V.
In really application, the Output pin could be accidentally connected to 16V (>3.3V) or -16V external unregulated battery. Customer's...
Give you only three voltage A, B, and C, no other voltage available. That means you don't know which one can be used as supply voltage for decision circuit. The other difficult part is that at certain time A could be the smallest voltage, while at other time B or C could be smallest voltage...
break a mosfet
Hi, All,
I'm using a CMOS process, in which there are two types of NMOS devices with the same gate oxide thickness. But their gate-source break down voltages are different. Why it is like that? Thanks for any information.
Re: Op Amp output protection
Thanks for your reply. My design requires that output should be tri-state if output is connected to voltage within the range from 6-16V or from 0V to -16V
output protection mos
In my process, there are some 18V devices, like DMOS, or PMOS/NMOS with source and drain extended. The thing is my op amp output swing is 10% to 90% of VDD.
op-amp with protection
Hi, All,
In my design, there are three pins: Vdd, Vss and Out. Vdd=5V, Vss=0, Out pin is driven by an internal op amp and its normal swing range is from 0.5V to 4.5V.
In the application, this Out pin can be accidentally connected to a voltage within the range from 0V...
snapback voltage
In the process specification, the NMOS breakdown voltage is 7V. Testing case is that NMOS length is 0.6uM, gate, source and substrate are connected to ground, then sweep drain voltage till drain take 1uA current. Process supply is 5V
In my design, I have to take care of...
CIrcuit is very simple, just 1st-order low pass RC filter. If I use R and C from analogLib library, which give ideal R and C value. I got the -3dB bandwidth fc1. If I use R and C from my technology library with the same R and C value and model is typical, I got another -3dB bandwidth fc2. And...
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