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Recent content by thriller_wu

  1. T

    Hi,i want to know how to write good testbench,thank you!

    Why not use SystemC write testbench? I think the performance is the highest priority in large design.
  2. T

    Cadence has acquired Verisity

    I thinks Cadence will acquire CoWare next step.
  3. T

    is synopsys going to port vcs to NT?

    Linux platform is better than windows nt.
  4. T

    Alert:Design reuse is good to employer but evil to employee

    In million-gate asic design, no design resue is incredibly.Software code can be resue more than hardware design, do u think programmer lost his job?
  5. T

    Will Specman die for Vera as Borland die for Micro$oft?

    But I think specman will beat vera. Vera is tooooo slow.
  6. T

    problem of vcs on linux2.4

    Why not try Redhat 8.0? It will be ok.
  7. T

    VHDL/Verilog Editor under Linux

    vhdl verilog linux vi is the best editor in unix/linux. And i hate syntax highlight. :)
  8. T

    To find books on Linux kernel

    Very good. But I have no time to read. Useless. Warning!
  9. T

    problem of vcs on linux2.4

    Recompile your linux kernel maybe resolve the issue. I can use VCS7.0 on Redhat 8.0. Please check you gcc and ld version.
  10. T

    will 64 bit system support mentor and cadence product

    cadence support 64bit mode in ncverilog if you use -64bit.
  11. T

    how much this EDA Tools Cost

    Very expensive if you buy all of the tools. And you should know what the feature you want.Don't have overlap function if you buy them.
  12. T

    setup, hold, recovery, removal time

    setup time hold time recovery time I think you can find answer in synospys sold.
  13. T

    What is better for a digital designer: Cadence or Synopsis?

    cadence vs synopsys I thinks VCS is better than ncverilog
  14. T

    Writing testbench in verilog or e language?

    I think use verification language to build testbench will be better.But verilog will be faster when running simulation.
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