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tcsh srand
Hi
I have a question about C shell script.
How to randomise the value of a variable in C shell (tcsh) script? is there a rand() or srand() command like in C?
Thanks.
When I write a foreach loop as below:
#######################################
#!/bin/tcsh -f
foreach file (\
a\
b\
c\
)
commands
.......
......
......
end
exit 0
################################
The script always executes the first file (a) only, after that it will report a message:
"Too...
modelsim time unit
I am using the evaluation version of ModelSim SE. I want to edit the modelsim.ini file, but I am not sure where I can find it . Can somebody help?
Re: C to RTL tools
Hi, you mean the area synthesized for RTL generated with such tools will be much bigger than manually coded RTL? Have you tried with one or some of such tools?
Re: C to RTL tools
Hi thanks for your reply...
I think at the moment, these tools are still unable to replace manually coded RTL in terms of quality....... but heard that it can shorten a lot the time needed for design.......
Re: C to RTL tools
how's the performance of the tools mentioned above? I mean compare with hand coded RTL.
Ever heard of tools from Synfora and Y Explorations Inc.?
Another question:
I run a synthesis with 2 compile.
The first compile is run withou any option, and the "check_design" command reports some warnings.
After that, the compiled design is "ungroup -flatten -all" and then compile again with options...
Hi,
I coded some registers in my RTL. But after I synthesized it with DC, I can't find one of the registers in the gate level netlist generated.
May I know the possible reason this kind of problem happen?
parallel case directive
The version of DC I am using is 2003.06-SP1, I ran synthesis for a module which contains two case, and each case contains 4 to 5 statements. Both of the synthesis (the module with and without the "//synopsys parallel_case" directive) result , in terms of timing or area...
synopsys full and parallel cases
I found some explaination from synopsys website about the warning occured.
>Problem:
>
>
>During elaboration, Design Compiler reports the following message:>
>
>Warning: /home/design/test.v:12: Case statement is not a parallel >case.
>(ELAB-910)
>
>The case...
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