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Quick logic Pune have few requirements in ASIC design for fresher level... look ahead .. and submit your CV with good projects .. too..
Wish U good luck.....
Please tell me the possible solution for tetra max,,, whenever I am opening GUI window of tetra max then getting message after opening kernel not supported GUI has to exit.
using kernel 2.6.18 centos 5.4
Thanks in advance ....
I installed IC61 in RHEL 5.4 but Unable to Invoke virtuoso as said by you in defined environment file for csh
please tell me how can I write cshrc for MMSIM with IC61 and please check how can I resolve the below error during invoking of tool.
command :spectremdl
Error :
Can’t load...
Installation help in HSpice 2010 in Centos 5.6
can anybody help me to resolve this issue in centos 5.6
getting error during installation of Hspice through the installer
If all the information is correct, continue with the installation.
Install? [yes]:
error writing "file5": broken pipe...
Since current mirrors give exact replica of input when both devices have same Vgs and they must operate in saturation region, (with channel length modulation neglected, and same sizing)
So can we operate Current mirrors in linear region by some modification or what parameters I need to keep in...
I want to know what is technology porting from one technology to another .
How this can be done.?
What are the constraints and criteria that need to consider during porting of design?
What are the drawbacks and advantages of porting?
Can anybody help on this ..
Thanks in advance
Hi,
can anybody explain how I do sizing of CMOS level shifter by cross coupled pmos transistors.
The model file is attached and I want to shift level 1.8 to 3.3 volts.
Thanks
Hello Friends,
I am getting problem when I open virtuoso in RHEL 4.0 of version 6.13
the error is
*ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
can anybody explain how can I resolve this problem.
Thanks in advance ..
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