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Recent content by telangamey_ei

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    [SOLVED] Difference in Combo Loop & Latch

    Hi, Thanks for your time & explanation. So, I think it's depend on how one can put it across. Regarding Unstable Memory based combo loop I think JK latch is a good example for "11" input. Thanks
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    [SOLVED] Difference in Combo Loop & Latch

    Hi, Thanks for your reply. So lets conclude. Please correct me if I am wrong. There are two types of combo loop & they are further sub-divided in two class:- a) Memory based Combo Loop a.1) Stable a.2) Unstable b) Memory Less Combo Loop b.1) Stable b.2) Unstable Acceptable...
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    [SOLVED] Difference in Combo Loop & Latch

    Hi Ads, Thanks for you reply. I know both are not good for FPGA/ ASIC design. But I am still confused:- #1. What if I write "assign q = rst ? d : q;" still it infer Latch with a combo loop inside it. But this time it has no clock. It doesn't matter the design has clock or not it's the way the...
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    [SOLVED] Difference in Combo Loop & Latch

    Hi, I am confused with the term combo loop & latch. When will tool suppose to generate a combo loop & when a latch? For ex:- The code shown below generates the Latch as per my understanding but few of the techies were not satisfied with my reply & they said me it's a combo loop:- assign q...
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    [SOLVED] .mem file reading byte by byte in tcl

    OK.... here is the peace of code which does this job. It reads line # 64, 128, 192 ...... & so on till EOF & reads initial 1 byte out of those lines. Pasting it below if someone needs in future. set fp [open "F:/test_tcl/mem.ini" r] set out [open "F:/test_tcl/mem_wr.ini" w] set count 0 set...
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    [SOLVED] .mem file reading byte by byte in tcl

    Hi ads-ee , Thanks for your such a nice & detailed explanation. This helps me to cross one ladder & I am able to read from my file byte by byte. The another challenge here is rather than reading from every line I want it to be read from specific sets of line. For Ex:- I have a text file...
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    [SOLVED] .mem file reading byte by byte in tcl

    Hi, I write something like this set f [open "F:/test_tcl/mem.ini" r] set out [open "F:/test_tcl/mem_wr.ini" w] seek $f 0 set s [read $f 2] puts $out "$s" seek $f 2 set s [read $f 2] puts $out "$s" seek $f 4 set s [read $f 2] puts $out "$s" seek $f 6 set s [read $f 2] puts $out "$s" seek $f 9...
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    [SOLVED] .mem file reading byte by byte in tcl

    Hi Paul, I understand there is no spoon feeding on this forum, but being a new bee to TCL I want to try this out. I searched a lot but not able to find out proper replies. I tried with "Split" command & creating different "for loops" but nothing work out. Even some kind of flow diagram...
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    [SOLVED] .mem file reading byte by byte in tcl

    Hi, I have a .mem file with for ex. below hex data in it ---------------------- ABCDEF11 22334455 ---------------------- Now, I want to read only 1 byte at a time (i.e. First time AB, second time CD & so on) till my data end. I want this to be done in TCL. Can some one please provide me an...
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    256b/257b transcoder in 100G Ethernet

    Hi, Could anyone explain what is the purpose of 256b/257b transcoder in 100G Ethernet again when we already performed 64/66b encoding. Thanks
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    Difference between various terms used in system verilog

    Thanks Dave for your reply. I understand that each component is separated in S.V. to make it more re-usable. But what every component should content & what it suppose to do? I am looking out for this explanation. Could you please help to elaborate each component content & meaning? Thanks
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    Difference between various terms used in system verilog

    Hi, I am new to System Verilog and just started reading it. I am confused with the following terms:- #1. Test, Generator, Agent & Driver this all looks same to me, what exactly is the difference in all of them. #2. Similarly what is the difference in Score Board, Checker, Assertions & Monitor...
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    What kind of reset do FPGA D F/F have?

    Hi, Sorry for the delay, I am engaged in the project with hammer over my head and got relief today. First again thanks for your support. I am referring to SPARTAN 6 UG384. https://www.xilinx.com/support/documentation/user_guides/ug384.pdf I went through couple of pages and I feel that it is...
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    What kind of reset do FPGA D F/F have?

    --------------------------------------------------------------------------------------------------------------------------------------------------------------- Hi, Thanks for your reply. Some how I am not able to find this description in any new FPGA data sheets. But your post helps me to...
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    What kind of reset do FPGA D F/F have?

    Hi, This is a very general question but I am not able to find a proper answer to it. May be I am not able to search it properly but it confuses me a lot. My point is simple, What kind of a Flop do FPGA have in its SLICES? I know its D F/F but the point is what kind of a reset do they have...
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