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I am interesting in distributed hardware architectures.
Especially:
- what kind of software/hardware can be synthesized in a distributed manner
- what are the current challenges in the field of synthesis of distributed systems
Currently I am working on automatic synthesis of...
Hello,
Please clarify the following misunderstanding:
according to the numerous layouts of cells (ex. here)
diff layout extends from source to drain, But if we look at transistor picture
we will see that diff layer is placed only around source (drain) contacts.
Ok, we may suppose that on the...
yes, i think so too, especially for a general case.
about the particular case of finding leakage through two closed sequential transistors there is an article on nangate site.
but in this article transistors are represented by quite rough analytical models.
thanks for the book:-)
fast spice algorithms
Thanks.
well, in fact, i have already an electronic version of "Inside Spice" by Ron M. Kielkowski (nevertheless, if it is not difficult, can you share "the spice book" or send to airat.halimov [at gmail.com]?).
spice algorithm nodal
ok, agree, the question looks strange.
well, by "SPICE algorithm" i mean the following process:
iterative loop
{
linearization and creation of matrix
solving equation
converged?
}
Are there any methods for DC analysis without "linearization" phase?
May be not so...
spice algorithms
Hello, every one,
do you know alternatives to SPICE algorithms for digital circuit simulation?
links or names of articles?
great thanks!
Hi, there,
Is a signal race in digital circuit an example of poor design?
Example: two different signals are propagated through the circuit. The final state depends on the signal that reach a destination first. After the first signal have reached the destination the circuit set up into stable...
Hi, there,
question arised:
how state-dependent leakages are calculated? (dependent on previous states)
Ex: lets consider FF.
This is a piece of Liberty file describing flip-flop cell:
cell(DBFRBN) {
area : 19.00;
cell_footprint : "DBFRB" ;
ff(IQ, IQN) {
next_state : "D"...
oh, yes : there is no signal in simulated file named "in". in fact, it is gate, and as you can see from spice file it is always VDD.
purpose of simulation is to understand..
on output should be 0 but I always watch VDD:
gate = VDD, transistor is NMOS => open transistor => V(drain) ~ v(source)...
n_12_hsl130e resistance
when simulated this spice circuit I have got the obscure result:
output is equal to 1.2 and 1.7.
But it seems to be 0 (open nmos transistor).
What is wrong?
info:
simulated with hsim,
spice file:
**********************************************
.lib...
you can see world is changing: GPU, nano, social, ...
is time accelerating?
what do you think, silicon will save your current positions disappear like dinosaurs?
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