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Recent content by taoshen

  1. T

    how much are it default value of enumeration in vhdl?

    how to decid the synthese mode?
  2. T

    Question about conversion direction

    Re: conversion question Can you give me a example that "OR using signal outside process " ?
  3. T

    Question about conversion direction

    Re: conversion question nand_gates : signal ----> wire if you are doing port mapping OR using signal outside process ================================= Are you meanings that the "wire" denotes the signal that can communicate among processes in one entity ?
  4. T

    Question about conversion direction

    conversion question I think that vhdl ------------------ verilog variable -----------------> reg signal ------------------> wire process -------------------> always May I be right?
  5. T

    is it difference between non-blocking and blocking in vhdl

    example ==================== signal var, v; variable branch; ... branch := '0'; var(31 downto 0) <= v(31 downto 0) ; ===================== There express the meaning of blocking or non-blocking ?
  6. T

    how much are it default value of enumeration in vhdl?

    example: ========================== type multypes is (none, iterative, m32x8, m16x16, m32x16, m32x32) ============================= value of none is 0 , 00, or 000 ? value of iterative is 01, 001 or 0001?
  7. T

    conversion of " and not " with verilog

    Thank jelydonut for kind help. : ) excuse me,thesr is another puzzling question about is_x ========================== pc : std_logic_vector(31 downto 0); ... if not is_x(pc) then ... ========================== The "is_x" means that each bit of the vector are "x" or some of the vector are...
  8. T

    conversion of " and not " with verilog

    in a vhdl file, there are the two following expression: =========================== variable tt : std_logic_vector(7 downto 0); ... tt := (others => '-' ); if ( exp1 and not exp2 ） =========================== how to express the same meaning of "-" and " and not " with VerilogHDL.
  9. T

    type constructs in vhdl is corresponding what in verilog

    type constructs in vhdl is corresponding what in verilog? wire in verilog is corresponding what in vhdl ?
  10. T

    whether Voice-crosstalk need to be considered ?

    I has been designed a soc . I plan to implement it with FPGA. Whether some frequent questions showed in back-end IC designs, for exmaple IR-drop,Voice-crosstalk, need to be considered ?
  11. T

    Are the designs method between FPGA and ASIC similar?

    right ? Hello everyone I has been designing a SoC with FPGA now. There are a puzzle where the differences of SoC designing methodology between by fpga and by IC(asic),which have been stayed in my brain All the two methods need ip-core(hdl code).And differently, Soc implemented by fpga not...
  12. T

    The difference between simulation and synthesis

    simulation and synthesis what's diffenerce there are between Simulation and synthesis?
  13. T

    one fpga designe question

    I don't quite clear about some softs functions in this SoC design flow. Modsim-Xe-5.7 and ISE-6.1 can be suitable for forepart design ,for example coding and simulating . protel can finish back-end desing, for example layout. what do these tools that Design Compiler and PrimeTime (synopsys...
  14. T

    one fpga designe question

    hi , I want to design one Soc development board based the complex of virtex FPGA and architecture ARM processor ,which provides a platform for implementation new designs. There are two questions puzzled me .1) what's part do the FPGA device may act ? 2>and ,if the part is decided ,whether the...
  15. T

    How to debug verilog code

    debug the verilog codings How to debug the code of verilog ! what tools need to be used! Excuse me! I'm freshman .This question is very baby! Update: The above expression may be not clear . it should be how to compile verilog code.
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