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Xilinx ISE 8.1i gives me this message:
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <vid_byp_reg1<0>> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic...
could not find module primitive coregen
I just created a math core to calculate division/remainder. I wanted to copy the declaration codes to my verilog file from the language template as I did before. But it's empty, and coregen didn't create any .v file. The VHDL files are normal. What's...
verilog mod operator
Xilinx ISE 8.1
My codes are simply
if (A % B > ***)
....................
Added after 5 minutes:
Thanks. It seems it's impossible to use modulus/division operators. :(
The range of my operands is too large for a lookup table. I will try math core.
verilog modulo operator
I got this error "Operator % is only supported when the second operand is a power of 2." My second operand is a integer constant. Is it synthesizable? I have to use this operator.
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