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I have a digital ic deaign experience around 12 years include graduated school.
I worked 8 years world No. 1 semiconductor company.
possible
1. RTL design , Synthesis, STA and p&r by synopsys tool
2. Design a testchip for ip verification.( IO, i2c, spi interface)
3. Digital logic in Analog...
I used that constraint in DC.
And I extracted sdc from DC.
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set_input_delay -clock U_DIGITAL_DUALEDGE_TOP/I_CLK -min 1 [get_pins U_DIGITAL_DUALEDGE_TOP/I_RISE]
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And it works at Primetime.
Anyone know?
Hello I am synthesis chip.
When I use dc,
I used this constraint.
-------------------------
set_input_delay -min 1 [get_ports U_DIGITAL_DUALEDGE_TOP/I_RISE] -clock U_DIGITAL_DUALEDGE_TOP/I_CLK
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but when I use thay constraint in primetime.
I got this message...
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