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I've been struggling with Altium and can't find a rule-set that seems to let me do what I want: I want the plane-swell (clearance) around thru-board signal vias to be 9 mil on GND layer but 14 mil on PWR plane layers. This was easy to do in PCAD but seems impossible in Altium. Any ideas...
just make sure if there are any current requirements on the net, that you don't accidentally let current go in pin-1 and out pin-2 in excess of the part's capacity. Since the tool will let you route half your net to pin-1 and the other half to pin-2 and consider it fully routed through the...
better to make it two separate parts, and either manually control the BOM, or use the 'Variants' feature. If one is going to dominate production it's simple to make the other be a non-BOM type component. Just know to populate the opposite for those oddball prototypes.
You can also just do the...
I can't remember if pcad had the auto-fan-out tool like Altium. One way is to just make a single 45 wire and via on pad A1. Then copy-paste-array for R/2 (R = number of rows). Copy-paste-array again for R/2 in the other dimension to get a full quadrant of the chip. Then simple copy paste...
For the component, or entire design, edit the 3d body model. You can select either the bounding box, or the actual object made by just the lines, of any single layer, and have this define the 3d body. (The body itself can exist on another dedicated mech layer too.) So you can select just silk...
Altium has options to let higher level net names take priority, let power port names take priority. It does not, unfortunately let you decide in what order these options take effect. Some Aussie programmer just went off and assumed on your behalf that if both are checked that you MUST have...
One thing that got me recently is that you can't just have a yellow port named Test[1..x] and a thick blue wire, and off that a singleton net Test1. You must also have a net label on the thick blue bus wire named Test[1..x].
It's not realizing that Test1 and the port are related. Singleton...
You effectively want anti-thermal-gap-pad. :-P
They do make foam strips with adhesive on one or both sides (such as 'padded' double sided tape.) May not be intended as an insulator but could work. Adhesive would hold it in place while the resin was poured. Or tacking down a piece of foam or...
The two designs would need to be the same number of layers (and dielectric thicknesses per layer, if you are specing that out.) Also, you'll be paying the cost of whichever board has the smallest feature sizes across both. If you are already doing N-up on a panel, the fab house might be able to...
Looks like you got lucky and they missed all the copper signals, just the bottom layer pour/plane. If there is the potential of something pressing against the board in those spots and shorting to that plane, then some dielectric (kapton tape would do) to cover. But seeing as you have non-zero...
I haven't used bus pins for components. If that could even possibly be it, a debugging step would be to break it out into normal pins.
In-re pic #3: I think that the wire label and the bus label must match each other exactly (except for the index number at the end). But don't NEED to match...
Something with low overhead might be to store the parameters for all possible chips in the 'bunch' in the bit file as array(s). Then use a few otherwise unused I/O pins to statically code for "which chip/function/ID am I?" Then your parameters := PARAM_ARRAY(to_unsigned(IdPins(5 downto 0));
Note that this will require a re-compile/synth/PAR for each chip leading to a unique bitstream per chip. If the devices are actually identical except for a few parameters, one solution might be to allow those parameters to be loaded* after configuration and power-on-reset, but before the chip...
Note that the OP's approach has some drawbacks. What happens when input and clk both have a rising edge EXTREMELY close to each other? I.e. a race condition. Output is then not well defined. You might get a 99.9% clk period pulse, or you might get a non-digital runt of a pulse a the output...
That's fine for a flag/pulse type signal that has a 'default' value most of the time. Particularly if it is only sparsely set to a non-default in the if/then/else tree. Which is most likely the case for a signal with a name like that.
Of course if this was being used as a state variable/bit...
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