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Hi,
I have a bandgap and I want to know how can I be sure that it is stable.
I know that the negative feedback must be "stronger" than positive feedback but how can I check this ?
I have 2 bode plots , one for positive loop and one for negative loop.
I have to subtract the dB values of the 2...
you should loot at the model file of your technology.
there it will be a section where all the corners are defined. You will notice that there are few parameters that change for each corner. (usually between 3 and 20).
All the other model parameters are kept the same for all corners.
So if you...
thanks but your proposed method give errors if the DC gain is less than infinite.
For a simple S/H (ideal switch and capacitor) is ok since the at the end of sampling time the Vo will go asymptotically to Vin.
But if there is any gain involved, the DC gain will affect the ratio Vo/Vin. So for...
in Viva/Wavescan (but also in ADW) you can change the X axis with the signal that you want. For example you have to save the input signal (the voltage ramp that you put at the ADC input.
Then you plot the transient with output codes and the input voltage on the same graph. It must be the same...
I want to make a Sample and hold circuit.
I want to know if there is a way to simulate and plot graphically the number of time constants.
To be more specific : I know from behavioral model that 1 time constant is max 30ns. The Tsample is 250ns. So the minimum UGF is 1/(2pi*tau)=5.3MHz.
But if...
Re: ESD at the SW pin
A pin that has a big power transistor is well protected. that transistor is in fact better than a simple ESD protection because is bigger in area and low resistive. That's why usualy the switching pins don't need a ESD structure (excepting some special cases).
But be...
Re: Simple HSPICE Question
.include XXX.xyz is a general thing. With this you can include any tipe of file (for example a netlist, or some other code). The inclusion is complitely blind and the inclusion is made exactly on the point you inserted the .include statement.
With .lib YYY.xyz ...
Re: VDS
With a stacked MOS transistors you must take care only to the fact that all transistors must be in saturation (for example if they are used like a current mirror).
For example for a Nmos structure:
Start with the one from bellow. The one that is connected directly to GND.
Choose...
cmos vdssat
You rise a interesting question.
Till now I didn't see a clear explication for this.
Usualy when I need a maximum voltage range (and a minimum Vds) I choose first the L in such a way to fit the noise/matching and after that I calculate the W to fit the necessary current...
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