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Hi frnds,
Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis.
I m using cadence rtl compiler for synthesis of standard cells in verilog. After doing successful synthesis it generates gate level netlist which i have to simulate to verify the...
Hi guys,
i still not get solution for buffer prevent in schematic.
I get to use some more attributes to preserve buffer.
"set_attribute preserve true {BUF1}"
"set_remove_assign_options -buffer_or_inverter BUF1"
but still i find net from input to output instead of buffer.
Plz anybody...
Hi,
Absolutely this "primitive_function" could not found after run same command.
Can u help me for any other attribute so that i can get buffer "BUF1" cell which is in my library into schematic.
Thank You.
Hi,
this below script causes error:
"set_attribute primitive_function design"
Error: : Invalid attribute name. [TUI-40] [set_attribute]
: 'primitive_function' is not a valid attribute.
: Use 'set_attribute -h' to see a list of all valid attributes that can be set...
Hi,
I have a problem with .tcl script in RTL Compiler cadence.
I have a libcells BUF1,BUF4,INV4,INV21,etc. I want to synthesis for all these cells. But problem is i cant get the correct script for these. When i run the script found error " invalid atribute name ...... "
Let me explain 1...
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