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Recent content by suresh_

  1. S

    RN4020 Bluetooth Low Energy module

    Hi Susan, Thanks for your reply. This is a beginner's question. I am working on the Android App Demo given in https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=rn-4020-pictail. I followed the same procedure as mentioned in the document, but I don't see the data...
  2. S

    RN4020 Bluetooth Low Energy module

    I just got a RN4020 Bluetooth Low Energy PICtail daughter card. I have some issues while working on the application examples. Please let me know if anyone of you have used this module. Thanks.
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    What is the meaning of 'dec' in this circuit simulation file?

    "dec" is a Type of Sweep when performing AC Analysis. It refers to Decade. Other types of sweep are Octave, Linear, etc. In LTspice, you can set it in the Edit -> Simulation Command -> AC Analysis.
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    Steps to convert MATLAB code to HDL or VHDL

    Re: MATLAB to HDL converter HDL Coder can be used to generate Verilog/VHDL codes for Altera/Xilinx FPGAs. https://www.mathworks.com/products/hdl-coder/
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    matlab command audiorecorder

    https://www.mathworks.com/help/matlab/ref/audiorecorder.record.html https://www.mathworks.com/help/matlab/import_export/record-and-play-audio.html#bsdl2em You can get these details using a simple Google search or MATLAB's Help function.
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    Assuming recursive instantiation. Modelsim

    Without commenting on the logic, I see that there is no semicolon for output c. Otherwise, it's simulating.
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    [SOLVED] Please Guide me for designing the circuit

    If you want to measure the distance of cable fault from Power Systems perspective, then you have to use a Distance Relay. A simple Google search for Distance Relays gives you an idea of how a distance relay works.
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    PSPICE optocoupler model for simulation

    https://www.vishay.com/optocouplers/related/#spice
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    How to calculate exp() and log() and root() without multiplication in verilog?

    @FvM: I think, using only adders (+/-), the required logic can be implemented using CORDIC. Please correct me if I am wrong. Of course, a look-up table approach would be the simple.
  10. S

    How to calculate exp() and log() and root() without multiplication in verilog?

    You can use CORDIC algorithm. Google search "Cordic log exp square root algorithms".
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    RTL Design and Verification remote job

    @ Tampler: I have seven years of experience (ASIC/FPGA design and verification, PCB/System design and validation). I worked on Verilog, System Verilog and have a knowledge of VMM methodology. Can my profile be considered? Thanks.
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