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The exact procedure is desribed in detail as follows:
1、generate the corresponding simulation module(post translate simulation module or post-PAR simulation model)
2、click simulate post-translate/post PAR model, enter modelsim
The result is that simulation of post-translate has no...
Thank you very much for the reply. The attached file is the source design of module wgn.v.
The signal noise_I corresponds to the scene wher input state[1:0]="00", where noise_Q when input state[1:0]="10".
Next is the exact waveform I watched from Chipscope.
To all professionals,
I am new to FPGA design and have tried all my best to solve the error, but it still turned to be a failure. Therefore, I post to obtain some guidance, hopefully.
In detail, I instantiate module wgn_noise for two times and obtain two output signals—wgn_noise_I and...
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