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Recent content by sunanda reddy

  1. S

    APB Bridge Based on AMBA 4.0

    Hi, Iam going to design APB bridge. My idea of implementation is 1) AXI Master will be the input and APB slave will be the output 2)internally in the DUT AXI slave is interfaced to APB Master Now my question is 1)Does ACLK will be independent of PCLK . 2)If it is independent how the read...
  2. S

    AXI throughput and latency

    Hi, no. of bits it relates to WDATA bits i huv taken WDATA[31:0] correct me if iam wrong Thanks and regards, sunanda
  3. S

    AXI throughput and latency

    Hi all, I huv designed verilog code for single master and single slave. Master is the output and Slave is the input. How to calculate throughput and latency?
  4. S

    axi master controller

    Hi i huv designed verilog code for single master and single slave for AMBA3 AXI now i want to calculate latency and throughput for axi rtl code will u plz help me?
  5. S

    axi master controller

    Hi, how to calculate axi latency and throughput?
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