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Hi All,
For my research purpose, I am in need of a tool that extracts netlist from Bitstream.
Is it possible to extract the netlist from the bitstream (.bit file) of all kinds of FPGAs?? I have read about the tool called “debit” tool proposed by Note et al. to generate the netlists from the...
Hi all,
Is it possible to read-back from an already programmed FPGA? If possible, kindly explain the technique with EDA-CAD tool support for this operation.
Thanks in advance.
I think this will not work out. Say, if the sampling frequency is lowered to 20 MHz i.e. 50 ns, then RO period should at least be double the sampling period, i.e. 100 ns. This method will ultimately increases the TRNG size, but not optimize it.
Hi All,
I want to generate a true random number in Actel ProAsic3 FPGA development board which operates at 48 MHz. I tried to implement it using ring oscillators (RO) and used the system clock i.e. 48 MHz as sampling frequency. As the sampling period is around 48 MHz => 21 ns, the RO period...
Can you kindly elaborate on how to find out the signal that will have high fan-out once its synthesized?? i.e. it will have high fan-in i.e. input logic cone and high fan-out i.e. output logic cone???
my intention to modify the internal nets was not to adjust the fan-outs.. it is introduce some control logic inside my design at appropriate place which is the fan-in and fan-out net.
Hi all,
Have a nice day !!
I may implement my digital design using FPGA. Once the design is synthesized, i may read the HDL netlist file to introduce some design modifications, but i want to insert the logic at high fan-in and also high-fanout internal nets. In this regard, i want to know "is...
Hi All,
Have a nice day !!!
I have a FSM with four states and multiple outputs, but the outputs should be random. To achieve this, is it possible to generate random Boolean functions of the state element bits?
Hi all,
Have a Nice day...
In most of FPGA design tools (e.g. Xilinx ISE, Quartus IDE, Libero IDE/SoC), there is an option to chose preferred language either as VHDL or VERILOG. Sometimes, i open a project with preferred language as VHDL and import some VERILOG files and run the tool. It...
Hi...
Have a Nice day..
For a FPGA (PROASIC3, Libero IDE v9.1) based digital design, I want to increase fan-out count of a net without changing the original functionality. So i instantiated a combination of AND and XOR gates with enable input with*that particular net (say net1) as mentioned...
Hi..
Good Day to all...
I read few articles presenting security threads associated with JTAG enabled PCB such as read-out secret data, modify state of authentic part, etc. I want to understand in-depth about any such attacks.
To understand the practicality of such attacks, i need a feedback...
Hi...
Good day to all....
I have two digital designs, if say with and without modification and i want to measure how much of structural mismatch is been introduced by my design modification.
Do any parameters measured using EDA tools such as Formal verification tools can be used to show...
HI,
Good day to all.
If suppose the HDL/ netlist code for FPGA design is obfuscated, how to understand it?? Is there any systematic procedure to perform it??
Thank you in advance.
Regards,
SUMATHI G.
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