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A wideband CMOS LNA is designed based on resistive shunt feedback, noise canceling technique. A gain control of 24dB is required from this LNA. However, only 8dB of gain control is implemented in the current design (through changing resistance in the feedback path) in order to address a <-8dB...
The technology that I am using is 65nm CMOS. The NF and linearity requirement is very tight. At high gain, the NF must be <2.2dB and IIP3 should be -2dBm (with 2 tone input set to -25dBm) typically.
Hi, had designed a CMOS LNA operating from 100MHz to 1 GHz using resistive feedback with noise cancelling technique. Required a gain control of 22dB for 1dB/step in this LNA and a 20dB for 1 dB/step attenuator before the mixer (ie, output of LNA). The loading for this LNA after the attenuator...
Hi, pancho_hideboo, really confusing, do not know if which document to follow. Had tried to follow close to the examples in the attached lecture notes below, don't see begin in case.
Hi, can we have several assign variables within a case or if else statement? Is there any skip statement in veriloga?
The function of this module is to select the gain and NF depending on the bits of g_ctl[i] if lna_en is "high", otherwise, the lna will be indicated as disabled.
syntax...
Hi, pancho_hideboo, had read thru your append. As I am new to this, sometimes I feel quite confusing on the syntax and limitation by veriloga as comapred to verilogams. Is there ways/helps that I can refer to check thru the code with description of errors clearly.
Added after 2 hours 6...
Hi, thank you for your advice. The function of this module is basically to take in 2 bits input from en, then determine the c value. The output will be V(in) when en<1:0>=00, 2*V(in) when en<1:0>=01, 3*V(in) when en<1:0>=10 and 4*V(in) when en<1:0>=11.
Had tried to clear the bus issue but...
Hi, so sorry, typo error in the message, the bracket is there in the veriloga coding.
As seen in the declaration, "in" is an input, en is then the bus.
Had written a small module as follows and errors prompt. Would appreciate if anyone can tell me what does the error means.
The objective is to pass the selection and ouput value accordingly. However, syntax errors shown:" Error found by spectre during SpectreHDL compile.
veriloga.va...
Had started to learn to write veriloga. However, had some problems for the following. Would appreciate if someone can help.
1) Is there any limit on the number of buses to be define for a module? Had added in 4 buses with a<1:0>, b<2:0>, c<2:0> and d<5:0> and syntax error occurs, showing...
Hi, anyone has any example/reference that I can refer to start and write verilogA model for LNA. The model must include frequency dependency. Had to get this done by end of Feb.
Thank you in advance.
Added after 9 minutes:
Please send me the path. The design must be done in cadence...
A Low-Power Ultra-Wideband CMOS True RMS Power Detector
Yijun Zhou; Chia, M.Y.-W.
Microwave Theory and Techniques, IEEE Transactions on
Volume 56, Issue 5, May 2008 Page(s):1052 - 1058
Digital Object Identifier 10.1109/TMTT.2008.921299
Thank you in advance.
Re: Anyone have experience in designing 2.4GHz RF Power Dete
Hi, kspalla, thank you for your reply. So sorry that I didn't put my requirement properly. I am now trying to design a true RMS power detector circuit using CMOS 90nm process in 2.4GHz application.
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