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please refer to 《IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System》 which can easily be obtained. If you have any question after you read it， let's talk about it.
The IR drop rang you should care is related to the library you are using. If your cells working at voltage outside the library, no data is valid for your STA or else.
tf and lef
Excuse me, shankar:
I think you have some mistake. LEF file can contain two part : tech infomation and MACRO infomation. What you talk about LEF is only one part of LEF's desription, the MACRO part. And another part the tech.lef which contains the basic process infomation is mostly...
Thank you for your attention:
sc_in<bool> i_rst_b;
int flag[4];
int buf1;
int buf2;
sc_signal<bool> w_start;
sc_signal<bool> w_update;
sc_signal<bool> w_drop;
SC_METHOD(gen_flags)
sensitive_pos<<w_start<<w_update<<w_drop;
sensitive_neg<<i_rst_b;
gen_flags()
{
if(!i_rst_b.read())...
the variables are assigned in methods, the methods sensitive at the posedges of some signals. sometimes,the variables changed ,but I cannot see any changes in the signals.
who knows the reason?
Re: Timing_Analysis
setup vio is related to the clock period, and hold time violation have nothing to do with the clock period. So increase the clock period can help setup violation, but never hold violation. It means the chip have setup violation is inferior but the chip have hold time...
Leakage power must be paid more attention in .13 and below tech. In the same design in the same nano level tech, different percent of hvt or svt cell used in the design may result in different power consumption.
I used the netlist synthesis by DC and the same library in Firtst Encounter.
Without any change(IPO or CTS), I get a very different power estimation report.
From DC the power report is :
Cell Internal Power = 23.9280 mW (84%)
Net Switching Power = 4.4078 mW (16%)...
synopsys develop differet library for different foundary in the same feature size.
I wonder if library work at this way: Design a common library then do some change due to the difference foundary's process. If so is there a common design rule use by synopsys and a design rule used by foundary?
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