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hi guys,
i observed in my design that there is significant difference between syn and place WNS and TNS.
why does syn has higher numbers of WNS,TNS compared to place.
DC_topo does some coarse placement for rc estimation,
1.does dc do more buffering than icc placement?
2.is the rc estimation...
hi ,
i want to use the min chip feature in icc,so i need some idea of how to enable and use it .the min feature is
"to Search for smallest routable die size
•Preserves floor planning investment
•Eliminates costly resizing iterations"
which helps in gatecount reduction.Has some one used this...
hi,
i have a port in a submoduleA and a net in submodule B,when i use
connect_net [get_nets tdsunit1/cs_ff_mode[31]] [get_ports teunit1/cs_ff_mode_31],its giving that they are in diff hierarchy and so cannot be connected.is there a way to create another net or something so that i can connect...
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