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Recent content by sudeep_

  1. S

    Digital-to-Analog Converter post silicon validation

    Its not any application. I have to measure the DAC perfromance (SNR, ENOB by applying digital signal) in the LAB. How to design a PCB schematic to communicate the Diaigl input pins of the DAC?
  2. S

    Digital-to-Analog Converter post silicon validation

    Post-silicon validation for Digital_to_Analog converter and Ideal PCB schematic for DAC
  3. S

    Digital-to-Analog Converter post silicon validation

    Hi, Could you tell me any process how to validate the Digital_to_Analog converter. Is there any method to communicate Digital signal and Digital Input of DAC. Thanks for comments..
  4. S

    DC offset cancellation circuit for high speed application circuits

    Hi, Can anyone suggest me DC offset cancellation circuit for high frequency application (50 MHz) circuits. I used the continuous time feedback model circuit include LPF+OTA, but it degrades the opamp gain and linearity at common mode output votlage range. I am not sure the sampling clock...
  5. S

    Why are the bandwidth and AC response different for Vpulse and Asia as inputs in a GmC filter?

    Why bandwidth and ac response is different for Vpulse and Vsin as input in GmC filter Hi, I used both vpulse and vsin to verify the GmC low pass filter in Cadence spectre, but the f-3dB bandwidth and ac response appears with different values. I set the ac magnitude for both signal is same...
  6. S

    [SOLVED] Switched Capcitor Integrator output saturation in Verilog ams

    Hi All, I used the simple Verilog ams code for simulating Switched Capcitor Integrator. I am not sure how to control the Inegrator output saturation in this code. Can anyone help in this case to add Integrator output bounds. module noninvert_integ(out, in, phi1, phi2); input in, phi1, phi2...
  7. S

    -3dB Bandwidth check for active cmos RC filter

    -3dB BW measurement for LPF. Which one is used for -3dB BW ( CL or loopgain plot)?
  8. S

    -3dB Bandwidth check for active cmos RC filter

    Could you elobarate this statement. "Hence, I see no reason to measure/calculate/simulate the 3dB BW not in this closed-loop configuration".
  9. S

    -3dB Bandwidth check for active cmos RC filter

    The circuit is designed as 2nd order Multiple feedback active cmos filter, I am not sure to check -3dB BW by considering Loop gain or Closed loop gain plot.
  10. S

    -3dB Bandwidth check for active cmos RC filter

    Can anyone tell me, which can be used for -3dB bandwidth check for active cmos filter using opamp like loop gain vs closed loop gain.
  11. S

    Commonmode feedback circuit poles compensation in differential Active RC Filter

    Hi, Can any one suggest me to remove the poles in CMFB circuit loop in differential opamp. This poles are appeared due to the filter feedback network. The CMFB circuit has shown below, and Loop gain and phse shift. I noticed that SR did not change in the Filter due to instability of CMFB.
  12. S

    How to choose -3dB filter bandwidth for an input signal frequency?

    If I set the BW at 40 MHz, the SR is dropped. If SR is setteled then BW of the Filter show at higher frequency. Moreover, the currents at Compensation Capcitor in Opamp is very low (swing < 80uA). But Input stage and output stage currents are 300uA, 800 uA. How to increase the Current swing...
  13. S

    How to choose -3dB filter bandwidth for an input signal frequency?

    Hi, I have one doubt on choosing filter Bandwidth. My input signal frequency is 40 MHz for an active RC filter. I don't know how to choose value of the -3dB BW. Is there any relation between the input signal freq versus BW? Thanks!
  14. S

    Operational amplifier with output buffer

    Operatioanl amplifier with output buffer for Active RC filter Hi, Can anyone provide more literature or docuemnt for Output buffer stage in Operational Amplifier for an Active RC filter. The buffer stage is using to drive the RC loads, I dont understand how to design the output buffer stage...
  15. S

    DC run and Trnasient Response in Cadence ADE

    Hi, Why the circuit showing differnt transient response from DC operating points for Op-AMP in Cadene ADE? If the circuit is keeping the values at a fixed DC operating points, the transeint signal moved to another common node voltage.
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