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@JEFFREY SAMUEL: This is part of my project...I was told to extend my project into ASIC domain once I'm done with the FPGA implementation of the segmentation algorithm, where I'll be using the code generated from system generator.
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Just wanted to know if it can be done...My...
I have written the spice code for a 1-bit SRAM cell with all its sub-blocks...I wanted to know how to calculate the write and read access time from the output waveforms?
I have designed a 3-stage VCO with 0.9V power supply with minimum frequency of 500MHz and maximum frequency of 8GHz. I have used the following SPICE commands which I took from a post https://www.edaboard.com/threads/127339/
.HBOSC tones=500e6 nharms=10 PROBENODE=fosc,0,0.45 FSPTS=20,500e6,8e9...
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